From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 31 Aug 2019 09:12:06 +0000 (+0200)
Subject: Fix TRELLIS_FF simulation model
X-Git-Tag: working-ls180~956^2~40^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3c16a05657e639a04d647a15af56b6fbce25e17;p=yosys.git

Fix TRELLIS_FF simulation model
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 75a1aad1f..5bdb8395e 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -229,14 +229,15 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter REGSET = "RESET";
 	parameter [127:0] LSRMODE = "LSR";
 
-	reg muxce;
-	always @(*)
+	wire muxce;
+	generate
 		case (CEMUX)
-			"1": muxce = 1'b1;
-			"0": muxce = 1'b0;
-			"INV": muxce = ~CE;
-			default: muxce = CE;
+			"1": assign muxce = 1'b1;
+			"0": assign muxce = 1'b0;
+			"INV": assign muxce = ~CE;
+			default: assign muxce = CE;
 		endcase
+	endgenerate
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;