From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 13 Feb 2022 14:25:44 +0000 (+0000)
Subject: not for any good reason, separate adding the uart16550 verilog source
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3c4783b2fc5a4ea5d22e1932a5e55da8f846d35;p=ls2.git

not for any good reason, separate adding the uart16550 verilog source
---

diff --git a/examples/ls2.py b/examples/ls2.py
index 09d4043..711299e 100644
--- a/examples/ls2.py
+++ b/examples/ls2.py
@@ -82,12 +82,7 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_000
 
         # UART
-        opencores_16550 = "../../uart16550/rtl/verilog"
-        pth = os.path.split(__file__)[0]
-        pth = os.path.join(pth, opencores_16550)
-        fname = os.path.abspath(pth)
-        print (fname)
-        self.uart = UART16550(verilog_src_dir=fname)
+        self.uart = UART16550()
         umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")
         #umap.add_resource(self._mem, name="mem", size=1<<5)
         self.uart.bus.memory_map = umap
@@ -148,6 +143,16 @@ class DDR3SoC(SoC, Elaboratable):
             # wire up the CPU interrupts
             comb += self.cpu.ip.eq(self.intc.ip)
 
+        # add uart16550 verilog source. assumes a directory
+        # structure where ls2 has been checked out in a common
+        # subdirectory as https://github.com/freecores/uart16550
+        opencores_16550 = "../../uart16550/rtl/verilog"
+        pth = os.path.split(__file__)[0]
+        pth = os.path.join(pth, opencores_16550)
+        fname = os.path.abspath(pth)
+        print (fname)
+        self.uart.add_verilog_source(fname, platform)
+
         return m