From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jun 2020 10:43:17 +0000 (+0100)
Subject: start new version of Pi2LSUI based on PortInterfaceBase
X-Git-Tag: div_pipeline~223
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3d71a5a5b6377d1e028131c75bc2474b117c8b3;p=soc.git

start new version of Pi2LSUI based on PortInterfaceBase
---

diff --git a/src/soc/experiment/pi2ls.py b/src/soc/experiment/pi2ls.py
index 32b9693d..f9059f05 100644
--- a/src/soc/experiment/pi2ls.py
+++ b/src/soc/experiment/pi2ls.py
@@ -25,12 +25,44 @@
 from soc.minerva.units.loadstore import LoadStoreUnitInterface
 from soc.experiment.pimem import PortInterface
 from soc.scoreboard.addr_match import LenExpand
+from soc.experiment.pimem import PortInterfaceBase
 from nmigen.utils import log2_int
 
 from nmigen import Elaboratable, Module, Signal
 
 
-class Pi2LSUI(Elaboratable):
+class Pi2LSUI(PortInterfaceBase):
+
+    def __init__(self, name, lsui=None,
+                             data_wid=64, mask_wid=8, addr_wid=48):
+        print ("pi2lsui reg mask addr", data_wid, mask_wid, addr_wid)
+        super().__init__(data_wid, addr_wid)
+        if lsui is None:
+            lsui = LoadStoreUnitInterface(addr_wid, self.addrbits, data_wid)
+        self.lsui = lsui
+
+    def set_wr_addr(self, m, addr, mask):
+        m.d.comb += self.lsui.x_mask_i.eq(mask)
+        m.d.comb += self.lsui.x_addr_i.eq(addr)
+
+    def set_rd_addr(self, m, addr, mask):
+        m.d.comb += self.lsui.x_mask_i.eq(mask)
+        m.d.comb += self.lsui.x_addr_i.eq(addr)
+
+    def set_wr_data(self, m, data, wen): # mask already done in addr setup
+        m.d.comb += self.lsui.x_st_data_i.eq(data)
+        return ~self.lsui.x_busy_o
+
+    def get_rd_data(self, m):
+        return self.lsui.m_ld_data_o, ~self.lsui.x_busy_o
+
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+
+        return m
+
+
+class Pi2LSUI1(Elaboratable):
 
     def __init__(self, name, pi=None, lsui=None,
                              data_wid=64, mask_wid=8, addr_wid=48):
diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index a3bffa86..35a4dc0c 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -139,7 +139,7 @@ class PortInterfaceBase(Elaboratable):
 
     @property
     def addrbits(self):
-        return log2_int(self.mem.regwid//8)
+        return log2_int(self.regwid//8)
 
     def splitaddr(self, addr):
         """split the address into top and bottom bits of the memory granularity
@@ -149,8 +149,8 @@ class PortInterfaceBase(Elaboratable):
     def connect_port(self, inport):
         return self.pi.connect_port(inport)
 
-    def set_wr_addr(self, m, addr): pass
-    def set_rd_addr(self, m, addr): pass
+    def set_wr_addr(self, m, addr, mask): pass
+    def set_rd_addr(self, m, addr, mask): pass
     def set_wr_data(self, m, data, wen): pass
     def get_rd_data(self, m): pass
 
@@ -193,7 +193,7 @@ class PortInterfaceBase(Elaboratable):
             comb += lenexp.len_i.eq(pi.data_len)
             comb += lenexp.addr_i.eq(lsbaddr)
             with m.If(pi.addr.ok & adrok_l.qn):
-                self.set_rd_addr(m, pi.addr.data) # addr ok, send thru
+                self.set_rd_addr(m, pi.addr.data, lenexp.lexp_o)
                 comb += pi.addr_ok_o.eq(1)  # acknowledge addr ok
                 sync += adrok_l.s.eq(1)       # and pull "ack" latch
 
@@ -297,7 +297,7 @@ class TestMemoryPortInterface(PortInterfaceBase):
         lsbaddr, msbaddr = self.splitaddr(addr)
         m.d.comb += self.mem.wrport.addr.eq(msbaddr)
 
-    def set_rd_addr(self, m, addr):
+    def set_rd_addr(self, m, addr, mask):
         lsbaddr, msbaddr = self.splitaddr(addr)
         m.d.comb += self.mem.rdport.addr.eq(msbaddr)