From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 6 Jun 2020 16:13:50 +0000 (+0100)
Subject: allow Mem in Simulator to be initialised
X-Git-Tag: div_pipeline~530
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a3e5c3b59fbdf581427de8e4d9e2aca6441b794c;p=soc.git

allow Mem in Simulator to be initialised
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 299b74c0..525b2b70 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -31,10 +31,13 @@ def create_args(reglist, extra=None):
 
 class Mem:
 
-    def __init__(self, bytes_per_word=8):
+    def __init__(self, bytes_per_word=8, initial_mem=None):
         self.mem = {}
         self.bytes_per_word = bytes_per_word
         self.word_log2 = math.ceil(math.log2(bytes_per_word))
+        if initial_mem:
+            for addr, (val, width) in initial_mem.items():
+                self.st(addr, val, width)
 
     def _get_shifter_mask(self, width, remainder):
         shifter = ((self.bytes_per_word - width) - remainder) * \
@@ -168,9 +171,14 @@ class SPR(dict):
 class ISACaller:
     # decoder2 - an instance of power_decoder2
     # regfile - a list of initial values for the registers
-    def __init__(self, decoder2, regfile, initial_sprs={}, initial_cr=0):
+    def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
+                       initial_mem=None):
+        if initial_sprs is None:
+            initial_sprs = {}
+        if initial_mem is None:
+            initial_mem = {}
         self.gpr = GPR(decoder2, regfile)
-        self.mem = Mem()
+        self.mem = Mem(initial_mem=initial_mem)
         self.pc = PC()
         self.spr = SPR(decoder2, initial_sprs)
         # TODO, needed here:
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index d8233402..69c9d0fc 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -198,6 +198,10 @@ class TestRunner(FHDLTestCase):
                     yield from self.iodef.check_cu_outputs(res, pdecode2,
                                                             sim, code)
 
+                    # sigh.  hard-coded.  test memory
+                    if self.funit == Function.LDST:
+                        print ("mem dump", sim.mem.mem)
+
         sim.add_sync_process(process)
 
         name = self.funit.name.lower()
diff --git a/src/soc/fu/compunits/test/test_ldst_compunit.py b/src/soc/fu/compunits/test/test_ldst_compunit.py
index 525f88a1..c91b2e5d 100644
--- a/src/soc/fu/compunits/test/test_ldst_compunit.py
+++ b/src/soc/fu/compunits/test/test_ldst_compunit.py
@@ -22,6 +22,7 @@ class LDSTTestRunner(TestRunner):
         """naming (res) must conform to LDSTFunctionUnit output regspec
         """
 
+        print ("check cu outputs", res)
         # RT
         out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
diff --git a/src/soc/fu/ldst/test/test_pipe_caller.py b/src/soc/fu/ldst/test/test_pipe_caller.py
index 9f2f0c09..adceb4cf 100644
--- a/src/soc/fu/ldst/test/test_pipe_caller.py
+++ b/src/soc/fu/ldst/test/test_pipe_caller.py
@@ -56,11 +56,22 @@ class LDSTTestCase(FHDLTestCase):
         super().__init__(name)
         self.test_name = name
 
-    def run_tst_program(self, prog, initial_regs=None, initial_sprs=None):
-        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
+    def run_tst_program(self, prog, initial_regs=None,
+                        initial_sprs=None, initial_mem=None):
+        tc = TestCase(prog, self.test_name, initial_regs, initial_sprs,
+                      mem=initial_mem)
         self.test_data.append(tc)
 
-    def test_load_store(self):
+    def test_1_load(self):
+        lst = ["lwz 3, 0(1)"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0x0004
+        initial_regs[2] = 0x0008
+        initial_mem = {0x0004: (0x1234, 4)}
+        self.run_tst_program(Program(lst), initial_regs,
+                             initial_mem=initial_mem)
+
+    def tst_2_load_store(self):
         lst = ["stw 2, 0(1)",
                "lwz 3, 0(1)"]
         initial_regs = [0] * 32
@@ -68,11 +79,3 @@ class LDSTTestCase(FHDLTestCase):
         initial_regs[2] = 0x0008
         self.run_tst_program(Program(lst), initial_regs)
 
-    def test_ilang(self):
-        pspec = LDSTPipeSpec(id_wid=2)
-        alu = LDSTBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=alu.ports())
-        with open("ldst_pipeline.il", "w") as f:
-            f.write(vl)
-
-
diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index bd8a35a5..246a51e1 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -1,5 +1,6 @@
 class TestCase:
-    def __init__(self, program, name, regs=None, sprs=None, cr=0):
+    def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None):
+
         self.program = program
         self.name = name
 
@@ -7,7 +8,9 @@ class TestCase:
             regs = [0] * 32
         if sprs is None:
             sprs = {}
+        if mem is None:
+            mem = {}
         self.regs = regs
         self.sprs = sprs
         self.cr = cr
-
+        self.mem = mem