From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Sep 2021 10:19:47 +0000 (+0100)
Subject: update explanatory comments on LD/ST exception handling
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a403894daaf0060f014b6f0faab1bbc15e099844;p=soc.git

update explanatory comments on LD/ST exception handling
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 743c28ba..b13b5ebe 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -895,10 +895,16 @@ class TestIssuerInternal(Elaboratable):
                 with m.If(~core_busy_o): # instruction done!
                     comb += exec_pc_o_valid.eq(1)
                     with m.If(exec_pc_i_ready):
-                        # when finished, synchronize with the simulator.
-                        # however, if there was an exception, the simulator
-                        # executes the trap directly, so don't signal in
-                        # this case.
+                        # when finished, indicate "done".
+                        # however, if there was an exception, the instruction
+                        # is *not* yet done.  this is an implementation
+                        # detail: we choose to implement exceptions by
+                        # taking the exception information from the LDST
+                        # unit, putting that *back* into the PowerDecoder2,
+                        # and *re-running the entire instruction*.
+                        # if we erroneously indicate "done" here, it is as if
+                        # there were *TWO* instructions:
+                        # 1) the failed LDST 2) a TRAP.
                         with m.If(~pdecode2.ldst_exc.happened):
                             comb += self.insn_done.eq(1)
                         m.next = "INSN_START"  # back to fetch