From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 30 May 2019 23:02:40 +0000 (-0700)
Subject: read_xaiger() to name box signals
X-Git-Tag: working-ls180~1208^2~229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a41553a86125d58a0811975aa8636388615ba239;p=yosys.git

read_xaiger() to name box signals
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7adfacb53..399e46737 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -689,23 +689,27 @@ void AigerReader::post_process()
                         RTLIL::Wire* w = box_module->wire(port_name);
                         log_assert(w);
                         RTLIL::SigSpec rhs;
+                        RTLIL::Wire* wire = nullptr;
                         for (int i = 0; i < GetSize(w); i++) {
                             if (w->port_input) {
                                 log_assert(static_cast<unsigned>(co_count) < outputs.size());
-                                RTLIL::Wire* wire = outputs[co_count++];
+                                wire = outputs[co_count++];
                                 log_assert(wire);
                                 log_assert(wire->port_output);
                                 wire->port_output = false;
-                                rhs.append(wire);
                             }
                             if (w->port_output) {
                                 log_assert(static_cast<unsigned>(pi_count + ci_count) < inputs.size());
-                                RTLIL::Wire* wire = inputs[pi_count + ci_count++];
+                                wire = inputs[pi_count + ci_count++];
                                 log_assert(wire);
                                 log_assert(wire->port_input);
                                 wire->port_input = false;
-                                rhs.append(wire);
                             }
+                            rhs.append(wire);
+                            if (GetSize(w) == 1)
+                                module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name))));
+                            else
+                                module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i)));
                         }
                         cell->setPort(port_name, rhs);
                     }