From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 11 May 2020 18:18:29 +0000 (+0100)
Subject: comments from discussion
X-Git-Tag: div_pipeline~1277
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a42c2eb59cbce50b0cae93f4b44c8d9a2ecd1de7;p=soc.git

comments from discussion
https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
---

diff --git a/src/soc/alu/input_stage.py b/src/soc/alu/input_stage.py
index 389954b5..37bc3317 100644
--- a/src/soc/alu/input_stage.py
+++ b/src/soc/alu/input_stage.py
@@ -38,6 +38,9 @@ class ALUInputStage(PipeModBase):
 
         ##### operand B #####
 
+        # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+        # remove this, just do self.o.b.eq(self.i.b) and move the
+        # immediate-detection into set_alu_inputs in the unit test
         # If there's an immediate, set the B operand to that
         with m.If(self.i.ctx.op.imm_data.imm_ok &
                   ~(self.i.ctx.op.insn_type == InternalOp.OP_RLC)):
diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index 6e6a69b2..55ce27d4 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -27,6 +27,10 @@ def get_rec_width(rec):
 
 def set_alu_inputs(alu, dec2, sim):
     inputs = []
+    # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
+    # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
+    # and place it into data_i.b
+
     reg3_ok = yield dec2.e.read_reg3.ok
     if reg3_ok:
         reg3_sel = yield dec2.e.read_reg3.data