From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 23 Sep 2021 14:21:38 +0000 (+0100)
Subject: add stfsux and unit test, code was there, needed adding to power_enums
X-Git-Tag: sv_maxu_works-initial~843
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a432dafa65df71b83a7bbf8ee466b69e0742785e;p=openpower-isa.git

add stfsux and unit test, code was there, needed adding to power_enums
---

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index f5789d86..d08350aa 100644
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -72,7 +72,7 @@ class DecoderTestCase(FHDLTestCase):
     def test_fp_single_ldst(self):
         """>>> lst = ["lfsx 1, 1, 0",   # load fp 1 from mem location 0
                       "stfsu 1, 16(1)", # store fp 1 into mem 0x10, update RA
-                      "lfsu 2, 0(1)",   # re-load from UPDATED r1
+                      "lfs 2, 0(1)",   # re-load from UPDATED r1
                      ]
         """
         lst = ["lfsx 1, 1, 0",
@@ -93,6 +93,39 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
             self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
 
+    def test_fp_single_ldst_update_idx(self):
+        """>>> lst = ["lfsx 1, 0, 0",   # load fp 1 from mem location 0
+                      "stfsux 1, 2, 1", # store fp 1 into mem 0x10, update RA
+                      "lfs 2, 0(2)",   # re-load from UPDATED r2
+                     ]
+        """
+        lst = ["lfsx 1, 0, 0",
+               "stfsux 1, 2, 1",
+               "lfs 2, 0(2)",
+                     ]
+        initial_mem = {0x0000: (0x42013333, 8),
+                       0x0008: (0x42026666, 8),
+                       0x0020: (0x1828384822324252, 8),
+                        }
+        # create an offset of 0x10 (2+3)
+        initial_regs = [0]*32
+        initial_regs[1] = 0x4
+        initial_regs[2] = 0xc
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_regs=initial_regs,
+                                                initial_mem=initial_mem)
+            print("FPR 1", sim.fpr(1))
+            print("FPR 2", sim.fpr(2))
+            print("GPR 1", sim.gpr(1)) # should be 0x4
+            print("GPR 2", sim.gpr(2)) # should be 0x10 due to update
+            print("mem dump")
+            print(sim.mem.dump())
+            self.assertEqual(sim.gpr(1), SelectableInt(0x4, 64))
+            self.assertEqual(sim.gpr(2), SelectableInt(0x10, 64))
+            self.assertEqual(sim.fpr(1), SelectableInt(0x4040266660000000, 64))
+            self.assertEqual(sim.fpr(2), SelectableInt(0x4040266660000000, 64))
+
     def test_fp_mv(self):
         """>>> lst = ["fmr 1, 2",
                      ]
diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index db854396..b24be863 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -320,7 +320,7 @@ _insns = [
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
-    "stfs", "stfsx", "stfsu", "stfux",                  # FP store single
+    "stfs", "stfsx", "stfsu", "stfux", "stfsux",        # FP store single
     "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double
     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",