From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Wed, 15 Jan 2020 09:47:17 +0000 (+0100)
Subject: aco: do not combine additions of DS instructions on GFX6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a445cb35bdf607857742a322576cd9763b1d67ea;p=mesa.git

aco: do not combine additions of DS instructions on GFX6

The offset field doesn't work as expected on GFX6.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3412>
---

diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp
index 224918c172f..d8e42d88b7d 100644
--- a/src/amd/compiler/aco_optimizer.cpp
+++ b/src/amd/compiler/aco_optimizer.cpp
@@ -787,7 +787,11 @@ void label_instruction(opt_ctx &ctx, Block& block, aco_ptr<Instruction>& instr)
          DS_instruction *ds = static_cast<DS_instruction *>(instr.get());
          Temp base;
          uint32_t offset;
-         if (i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) && base.regClass() == instr->operands[i].regClass() && instr->opcode != aco_opcode::ds_swizzle_b32) {
+         bool has_usable_ds_offset = ctx.program->chip_class >= GFX7;
+         if (has_usable_ds_offset &&
+             i == 0 && parse_base_offset(ctx, instr.get(), i, &base, &offset) &&
+             base.regClass() == instr->operands[i].regClass() &&
+             instr->opcode != aco_opcode::ds_swizzle_b32) {
             if (instr->opcode == aco_opcode::ds_write2_b32 || instr->opcode == aco_opcode::ds_read2_b32 ||
                 instr->opcode == aco_opcode::ds_write2_b64 || instr->opcode == aco_opcode::ds_read2_b64) {
                if (offset % 4 == 0 &&