From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Jul 2020 14:59:28 +0000 (+0100)
Subject: spelling error
X-Git-Tag: div_pipeline~19
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a44ef2542c5a8fc536120cb201da3b70806e53d2;p=soc.git

spelling error
---

diff --git a/src/soc/fu/mul/post_stage.py b/src/soc/fu/mul/post_stage.py
index 0fe957bd..1c144ad1 100644
--- a/src/soc/fu/mul/post_stage.py
+++ b/src/soc/fu/mul/post_stage.py
@@ -57,7 +57,7 @@ class MulMainStage3(PipeModBase):
                 # compute overflow
                 mul_ov = Signal(reset_less=True)
                 with m.If(is_32bit):
-                    m31 = mul_o[31:64] # yes really bits 31 to 63 (incl)
+                    m32 = mul_o[31:64] # yes really bits 31 to 63 (incl)
                     comb += mul_ov.eq(m32.bool() & ~m32.all())
                 with m.Else():
                     m64 = mul_o[63:128] # yes really bits 63 to 127 (incl)