From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Jun 2019 06:43:04 +0000 (+0100)
Subject: add in missing modules
X-Git-Tag: ls180-24jan2020~988
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4581fa66a7fe475c27c2cbe0973a9371fbf9d12;p=ieee754fpu.git

add in missing modules
---

diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py
index 44d5461a..fe1cc9de 100644
--- a/src/ieee754/fpcommon/denorm.py
+++ b/src/ieee754/fpcommon/denorm.py
@@ -61,8 +61,10 @@ class FPAddDeNormMod(FPState, Elaboratable):
         m = Module()
         m.submodules.denorm_in_a = self.i.a
         m.submodules.denorm_in_b = self.i.b
+        m.submodules.denorm_in_z = self.i.z
         m.submodules.denorm_out_a = self.o.a
         m.submodules.denorm_out_b = self.o.b
+        m.submodules.denorm_out_z = self.o.z
 
         with m.If(~self.i.out_do_z):
             # XXX hmmm, don't like repeating identical code
diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 130c5ec2..7a8831ce 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -42,6 +42,7 @@ class FPRoundMod(Elaboratable):
 
     def setup(self, m, i):
         m.submodules.roundz = self
+        m.submodules.round_out_z = self.i.z
         m.d.comb += self.i.eq(i)
 
     def elaborate(self, platform):