From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 00:48:34 +0000 (+0000)
Subject: create Fetch class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4647c592a6aa6c6fd85a790dc18811634dd1ded;p=rv32.git

create Fetch class
---

diff --git a/cpu.py b/cpu.py
index 4798574..d345a00 100644
--- a/cpu.py
+++ b/cpu.py
@@ -154,7 +154,6 @@ class M:
         self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
 
 class Misa:
-
     def __init__(self, comb, sync):
         self.comb = comb
         self.sync = sync
@@ -168,6 +167,17 @@ class Misa:
         self.comb += self.misa.eq(Cat(cl))
 
 
+class Fetch:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.action = Signal(fetch_action, name="fetch_action")
+        self.target_pc = Signal(32, name="fetch_target_pc")
+        self.output_pc = Signal(32, name="fetch_output_pc")
+        self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
+        self.output_state = Signal(fetch_output_state,name="fetch_output_state")
+
+
 class CPU(Module):
     """
     """
@@ -204,17 +214,11 @@ class CPU(Module):
         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
         return Case(funct3, c)
 
+    def get_fetch_action(self, ft, dc, load_store_misaligned, mi,
+                         branch_taken, misaligned_jump_target,
+                         csr_op_is_valid):
+        c = {}
     """
-    def get_fetch_action(self, fetch_output_state,
-        input `decode_action decode_action,
-        input load_store_misaligned,
-        input memory_interface_rw_address_valid,
-        input memory_interface_rw_wait,
-        input branch_taken,
-        input misaligned_jump_target,
-        input csr_op_is_valid
-        );
-    begin
         case(fetch_output_state)
         `fetch_output_state_empty:
             get_fetch_action = `fetch_action_default;
@@ -334,11 +338,7 @@ class CPU(Module):
                   )
         self.specials += mii
 
-        fetch_act = Signal(fetch_action)
-        fetch_target_pc = Signal(32)
-        fetch_output_pc = Signal(32)
-        fetch_output_instruction = Signal(32)
-        fetch_output_st = Signal(fetch_output_state)
+        ft = Fetch(self.comb, self.sync)
 
         fs = Instance("CPUFetchStage", name="fetch_stage",
             i_clk=ClockSignal(),
@@ -346,11 +346,11 @@ class CPU(Module):
             o_memory_interface_fetch_address = mi.fetch_address,
             i_memory_interface_fetch_data = mi.fetch_data,
             i_memory_interface_fetch_valid = mi.fetch_valid,
-            i_fetch_action = fetch_act,
-            i_target_pc = fetch_target_pc,
-            o_output_pc = fetch_output_pc,
-            o_output_instruction = fetch_output_instruction,
-            o_output_state = fetch_output_st,
+            i_fetch_action = ft.action,
+            i_target_pc = ft.target_pc,
+            o_output_pc = ft.output_pc,
+            o_output_instruction = ft.output_instruction,
+            o_output_state = ft.output_state,
             i_reset_vector = reset_vector,
             i_mtvec = mtvec,
         )
@@ -359,7 +359,7 @@ class CPU(Module):
         dc = Decoder()
 
         cd = Instance("CPUDecoder", name="decoder",
-            i_instruction = fetch_output_instruction,
+            i_instruction = ft.output_instruction,
             o_funct7 = dc.funct7,
             o_funct3 = dc.funct3,
             o_rd = dc.rd,
@@ -453,7 +453,7 @@ class CPU(Module):
         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 
         self.comb += mi.rw_active.eq(~self.reset
-                        & (fetch_output_st == fetch_output_state_valid)
+                        & (ft.output_state == fetch_output_state_valid)
                         & ~load_store_misaligned
                         & ((dc.act & (DA.load | DA.store)) != 0))
 
@@ -482,15 +482,15 @@ class CPU(Module):
         lui_auipc_result = Signal(32)
         self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
                                              dc.immediate,
-                                             dc.immediate + fetch_output_pc))
+                                             dc.immediate + ft.output_pc))
 
-        self.comb += fetch_target_pc.eq(Cat(0,
+        self.comb += ft.target_pc.eq(Cat(0,
                     Mux(dc.opcode != OP.jalr,
-                                fetch_output_pc[1:32],
+                                ft.output_pc[1:32],
                                 register_rs1[1:32] + dc.immediate[1:32])))
 
         misaligned_jump_target = Signal()
-        self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
+        self.comb += misaligned_jump_target.eq(ft.target_pc[1])
 
         branch_arg_a = Signal(32)
         branch_arg_b = Signal(32)