From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 29 Oct 2014 10:18:17 +0000 (+0800)
Subject: fhdl/verilog: fix tristate to instance connection
X-Git-Tag: 24jan2021_ls180~2099^2~273^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4782899f6d4ada60c54af187b5f1020dd2404e3;p=litex.git

fhdl/verilog: fix tristate to instance connection
---

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index c34b11bd..b4bd534e 100644
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -275,7 +275,7 @@ def _printinit(f, ios, ns):
 	signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
 		- ios \
 		- list_targets(f) \
-		- list_special_ios(f, False, True, False)
+		- list_special_ios(f, False, True, True)
 	if signals:
 		r += "initial begin\n"
 		for s in sorted(signals, key=lambda x: x.huid):