From: H.J. Lu <hongjiu.lu@intel.com>
Date: Mon, 22 Oct 2018 07:35:48 +0000 (+0000)
Subject: i386: Enable AVX512 memory broadcast for INT andnot
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a48be73babd27c9deabf099b7202643dd447c9dc;p=gcc.git

i386: Enable AVX512 memory broadcast for INT andnot

Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT andnot operations.

gcc/

	PR target/72782
	* config/i386/sse.md (*andnot<mode>3_bcst): New.

gcc/testsuite/

	PR target/72782
	* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
	* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
	* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
	* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
	* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.

From-SVN: r265370
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9b735458d7c..7b1a98b8fb4 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* config/i386/sse.md (*andnot<mode>3_bcst): New.
+
 2018-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/72782
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e991da96aee..ee73e1fdf80 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12102,6 +12102,19 @@
 	      ]
 	      (const_string "<sseinsnmode>")))])
 
+(define_insn "*andnot<mode>3_bcst"
+  [(set (match_operand:VI 0 "register_operand" "=v")
+	(and:VI
+	  (not:VI48_AVX512VL
+	     (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
+	  (vec_duplicate:VI48_AVX512VL
+	    (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+  "TARGET_AVX512F"
+  "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
+  [(set_attr "type" "sselog")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "<sseinsnmode>")])
+
 (define_insn "*andnot<mode>3_mask"
   [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
 	(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 43b0ab56ec1..27d1ab98718 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,15 @@
+2018-10-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR target/72782
+	* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
+	* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
+	* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
+	* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
+	* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
+	* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
+	* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
+	* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
+
 2018-10-22  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR target/72782
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
new file mode 100644
index 00000000000..1450d3c1914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
new file mode 100644
index 00000000000..c9d8a820295
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
new file mode 100644
index 00000000000..a9608ca095d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
new file mode 100644
index 00000000000..71751fc874c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
new file mode 100644
index 00000000000..d74c373d435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
new file mode 100644
index 00000000000..8211815dbbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
new file mode 100644
index 00000000000..0b084ae5f7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m128i
+foo (__m128i x, int *f)
+{
+  return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
new file mode 100644
index 00000000000..cd27b40ba44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m256i
+foo (__m256i x, int *f)
+{
+  return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
+}