From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 May 2020 19:01:29 +0000 (+0100)
Subject: add CR out decoder debug
X-Git-Tag: div_pipeline~972
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a49b6ce15b9f98634b7b38eccd33aa26f1243cbf;p=soc.git

add CR out decoder debug
---

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 7a074f5a..69292429 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -141,6 +141,9 @@ class PowerOp:
         if row['CR in'] == '1':
             import pdb; pdb.set_trace()
             print(row)
+        if row['CR out'] == '0':
+            import pdb; pdb.set_trace()
+            print(row)
         res = [self.function_unit.eq(Function[row['unit']]),
                self.form.eq(Form[row['form']]),
                self.internal_op.eq(InternalOp[row['internal op']]),