From: Jakub Jelinek <jakub@redhat.com>
Date: Wed, 18 May 2016 09:23:39 +0000 (+0200)
Subject: sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use constraint x instead of v in... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4f164221f46579656fced58ae6a55cb409c4443;p=gcc.git

sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use constraint x instead of v in second alternative, add avx512bw alternative.

	* config/i386/sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use
	constraint x instead of v in second alternative, add avx512bw
	alternative.

	* gcc.target/i386/avx512vl-vpshufb-3.c: New test.
	* gcc.target/i386/avx512bw-vpshufb-3.c: New test.

From-SVN: r236367
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c445cc8bb85..1db6f919e9c 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,9 @@
 2016-05-18  Jakub Jelinek  <jakub@redhat.com>
 
+	* config/i386/sse.md (<ssse3_avx2>_pshufb<mode>3<mask_name>): Use
+	constraint x instead of v in second alternative, add avx512bw
+	alternative.
+
 	* config/i386/sse.md (*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Use
 	constraint x instead of v in second alternative, add avx512bw
 	alternative.
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 83eee2c94c7..63ecf861d5d 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -14218,21 +14218,22 @@
    (set_attr "mode" "DI")])
 
 (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
-  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,v")
+  [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")
 	(unspec:VI1_AVX512
-	  [(match_operand:VI1_AVX512 1 "register_operand" "0,v")
-	   (match_operand:VI1_AVX512 2 "vector_operand" "xBm,vm")]
+	  [(match_operand:VI1_AVX512 1 "register_operand" "0,x,v")
+	   (match_operand:VI1_AVX512 2 "vector_operand" "xBm,xm,vm")]
 	  UNSPEC_PSHUFB))]
   "TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
   "@
    pshufb\t{%2, %0|%0, %2}
+   vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}
    vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
-  [(set_attr "isa" "noavx,avx")
+  [(set_attr "isa" "noavx,avx,avx512bw")
    (set_attr "type" "sselog1")
-   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix_data16" "1,*,*")
    (set_attr "prefix_extra" "1")
-   (set_attr "prefix" "orig,maybe_evex")
-   (set_attr "btver2_decode" "vector,vector")
+   (set_attr "prefix" "orig,maybe_evex,evex")
+   (set_attr "btver2_decode" "vector")
    (set_attr "mode" "<sseinsnmode>")])
 
 (define_insn "ssse3_pshufbv8qi3"
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e8ee6b159d8..b528d8f4776 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,8 @@
 2016-05-18  Jakub Jelinek  <jakub@redhat.com>
 
+	* gcc.target/i386/avx512vl-vpshufb-3.c: New test.
+	* gcc.target/i386/avx512bw-vpshufb-3.c: New test.
+
 	* gcc.target/i386/avx512vl-vpmulhrsw-3.c: New test.
 	* gcc.target/i386/avx512bw-vpmulhrsw-3.c: New test.
 
diff --git a/gcc/testsuite/gcc.target/i386/avx512bw-vpshufb-3.c b/gcc/testsuite/gcc.target/i386/avx512bw-vpshufb-3.c
new file mode 100644
index 00000000000..5c215ae4705
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512bw-vpshufb-3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+  register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  a = _mm_shuffle_epi8 (a, b);
+  asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler "vpshufb\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+  register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  a = _mm256_shuffle_epi8 (a, b);
+  asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler "vpshufb\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]\[^\n\r]*ymm1\[67]" } } */
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-vpshufb-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-vpshufb-3.c
new file mode 100644
index 00000000000..ffdfad5cb1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-vpshufb-3.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -mavx512vl -mno-avx512bw" } */
+
+#include <x86intrin.h>
+
+void
+f1 (__m128i x, __m128i y)
+{
+  register __m128i a __asm ("xmm16"), b __asm ("xmm17");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  a = _mm_shuffle_epi8 (a, b);
+  asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpshufb\[^\n\r]*xmm1\[67]" } } */
+
+void
+f2 (__m256i x, __m256i y)
+{
+  register __m256i a __asm ("xmm16"), b __asm ("xmm17");
+  a = x;
+  b = y;
+  asm volatile ("" : "+v" (a), "+v" (b));
+  a = _mm256_shuffle_epi8 (a, b);
+  asm volatile ("" : "+v" (a));
+}
+
+/* { dg-final { scan-assembler-not "vpshufb\[^\n\r]*ymm1\[67]" } } */