From: Jacob Lifshay <programmerjake@gmail.com>
Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700)
Subject: split out instructions from openpower/isa/stringldst.mdwn
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4f1e73ebc7788b3c5daf370fd4a172954242243;p=openpower-isa.git

split out instructions from openpower/isa/stringldst.mdwn
---

diff --git a/openpower/isa/stringldst.mdwn b/openpower/isa/stringldst.mdwn
index 6357c4e1..73098ffe 100644
--- a/openpower/isa/stringldst.mdwn
+++ b/openpower/isa/stringldst.mdwn
@@ -8,109 +8,10 @@
 <!-- storage locations or to initiate a long move between unaligned storage fields. -->
 
 
-# Load String Word Immediate
+[[!inline pagenames="openpower/isa/stringldst/lswi" raw="yes"]]
 
-X-Form
+[[!inline pagenames="openpower/isa/stringldst/lswx" raw="yes"]]
 
-* lswi RT,RA,NB
+[[!inline pagenames="openpower/isa/stringldst/stswi" raw="yes"]]
 
-Pseudo-code:
-
-    EA <- (RA|0)
-    if NB = 0 then n <-  32
-    else           n <-  NB
-    r <- RT - 1
-    i <- 32
-    do while n > 0
-        if i = 32 then
-            r <- (r + 1) % 32
-            GPR(r) <- 0
-        GPR(r)[i:i+7] <- MEM(EA, 1)
-        i <- i + 8
-        if i = 64 then i <- 32
-        EA <- EA + 1
-        n <- n - 1
-
-Special Registers Altered:
-
-    None
-
-# Load String Word Indexed
-
-X-Form
-
-* lswx RT,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    n <- XER[57:63]
-    r <- RT - 1
-    i <- 32
-    RT <- undefined([0]*64)
-    do while n > 0
-        if i = 32 then
-            r <-  (r + 1) % 32
-            GPR(r) <- 0
-        GPR(r)[i:i+7] <- MEM(EA, 1)
-        i <-  i + 8
-        if i = 64 then i <- 32
-        EA <-  EA + 1
-        n <- n - 1
-
-Special Registers Altered:
-
-    None
-
-# Store String Word Immediate
-
-X-Form
-
-* stswi RS,RA,NB
-
-Pseudo-code:
-
-    EA <- (RA|0)
-    if NB = 0 then n <-  32
-    else           n <-  NB
-    r <- RS - 1
-    i <- 32
-    do while n > 0
-      if i = 32 then r <-  (r + 1) % 32
-      MEM(EA, 1) <-  GPR(r)[i:i+7]
-      i <-  i + 8
-      if i = 64 then i <-  32
-      EA <-  EA + 1
-      n <- n - 1
-
-Special Registers Altered:
-
-    None
-
-# Store String Word Indexed
-
-X-Form
-
-* stswx RS,RA,RB
-
-Pseudo-code:
-
-    b <- (RA|0)
-    EA <- b + (RB)
-    n <- XER[57:63]
-    r <- RS - 1
-    i <- 32
-    do while n > 0
-      if i = 32 then r <- (r + 1) % 32
-      MEM(EA, 1) <- GPR(r)[i:i+7]
-      i <-  i + 8
-      if i = 64 then i <- 32
-      EA <-  EA + 1
-      n <- n - 1
-
-Special Registers Altered:
-
-    None
-
-<!-- Checked March 2021 -->
+[[!inline pagenames="openpower/isa/stringldst/stswx" raw="yes"]]
diff --git a/openpower/isa/stringldst/lswi.mdwn b/openpower/isa/stringldst/lswi.mdwn
new file mode 100644
index 00000000..401af556
--- /dev/null
+++ b/openpower/isa/stringldst/lswi.mdwn
@@ -0,0 +1,13 @@
+# Load String Word Immediate
+
+X-Form
+
+* lswi RT,RA,NB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/stringldst/lswi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/stringldst/lswi_code.mdwn b/openpower/isa/stringldst/lswi_code.mdwn
new file mode 100644
index 00000000..8fb6f3bb
--- /dev/null
+++ b/openpower/isa/stringldst/lswi_code.mdwn
@@ -0,0 +1,14 @@
+    EA <- (RA|0)
+    if NB = 0 then n <-  32
+    else           n <-  NB
+    r <- RT - 1
+    i <- 32
+    do while n > 0
+        if i = 32 then
+            r <- (r + 1) % 32
+            GPR(r) <- 0
+        GPR(r)[i:i+7] <- MEM(EA, 1)
+        i <- i + 8
+        if i = 64 then i <- 32
+        EA <- EA + 1
+        n <- n - 1
diff --git a/openpower/isa/stringldst/lswx.mdwn b/openpower/isa/stringldst/lswx.mdwn
new file mode 100644
index 00000000..ef7d8d06
--- /dev/null
+++ b/openpower/isa/stringldst/lswx.mdwn
@@ -0,0 +1,13 @@
+# Load String Word Indexed
+
+X-Form
+
+* lswx RT,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/stringldst/lswx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/stringldst/lswx_code.mdwn b/openpower/isa/stringldst/lswx_code.mdwn
new file mode 100644
index 00000000..d7cdfb5b
--- /dev/null
+++ b/openpower/isa/stringldst/lswx_code.mdwn
@@ -0,0 +1,15 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    n <- XER[57:63]
+    r <- RT - 1
+    i <- 32
+    RT <- undefined([0]*64)
+    do while n > 0
+        if i = 32 then
+            r <-  (r + 1) % 32
+            GPR(r) <- 0
+        GPR(r)[i:i+7] <- MEM(EA, 1)
+        i <-  i + 8
+        if i = 64 then i <- 32
+        EA <-  EA + 1
+        n <- n - 1
diff --git a/openpower/isa/stringldst/stswi.mdwn b/openpower/isa/stringldst/stswi.mdwn
new file mode 100644
index 00000000..90fbef9d
--- /dev/null
+++ b/openpower/isa/stringldst/stswi.mdwn
@@ -0,0 +1,13 @@
+# Store String Word Immediate
+
+X-Form
+
+* stswi RS,RA,NB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/stringldst/stswi_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
diff --git a/openpower/isa/stringldst/stswi_code.mdwn b/openpower/isa/stringldst/stswi_code.mdwn
new file mode 100644
index 00000000..633b6250
--- /dev/null
+++ b/openpower/isa/stringldst/stswi_code.mdwn
@@ -0,0 +1,12 @@
+    EA <- (RA|0)
+    if NB = 0 then n <-  32
+    else           n <-  NB
+    r <- RS - 1
+    i <- 32
+    do while n > 0
+      if i = 32 then r <-  (r + 1) % 32
+      MEM(EA, 1) <-  GPR(r)[i:i+7]
+      i <-  i + 8
+      if i = 64 then i <-  32
+      EA <-  EA + 1
+      n <- n - 1
diff --git a/openpower/isa/stringldst/stswx.mdwn b/openpower/isa/stringldst/stswx.mdwn
new file mode 100644
index 00000000..6f008fab
--- /dev/null
+++ b/openpower/isa/stringldst/stswx.mdwn
@@ -0,0 +1,15 @@
+# Store String Word Indexed
+
+X-Form
+
+* stswx RS,RA,RB
+
+Pseudo-code:
+
+[[!inline pagenames="openpower/isa/stringldst/stswx_code" raw="yes"]]
+
+Special Registers Altered:
+
+    None
+
+<!-- Checked March 2021 -->
diff --git a/openpower/isa/stringldst/stswx_code.mdwn b/openpower/isa/stringldst/stswx_code.mdwn
new file mode 100644
index 00000000..a593afb9
--- /dev/null
+++ b/openpower/isa/stringldst/stswx_code.mdwn
@@ -0,0 +1,12 @@
+    b <- (RA|0)
+    EA <- b + (RB)
+    n <- XER[57:63]
+    r <- RS - 1
+    i <- 32
+    do while n > 0
+      if i = 32 then r <- (r + 1) % 32
+      MEM(EA, 1) <- GPR(r)[i:i+7]
+      i <-  i + 8
+      if i = 64 then i <- 32
+      EA <-  EA + 1
+      n <- n - 1