From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 19:43:18 +0000 (-0700)
Subject: Extend test with renaming cells with prefix too
X-Git-Tag: working-ls180~1023^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4f2f7d23cb27f7677236d7a1823f36215c874e9;p=yosys.git

Extend test with renaming cells with prefix too
---

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index ee5c6bc7e..c2f42d50b 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -2,6 +2,7 @@ read_verilog <<EOT
 module sub(input i, output o, input j);
 foobar _TECHMAP_REPLACE_(i, o, j);
 wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
 endmodule
 EOT
 design -stash techmap
@@ -14,3 +15,4 @@ EOT
 
 techmap -map %techmap
 select -assert-any w:s0.asdf
+select -assert-any c:s0.blah