From: Wilco Dijkstra Date: Wed, 4 Dec 2019 14:45:59 +0000 (+0000) Subject: [AArch64] Add support for fused compare and branch X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4f3fa716f9fc6fbab40b5d247db60385c69cd90;p=gcc.git [AArch64] Add support for fused compare and branch Add support for fused compare with branch. Rename the existing AARCH64_FUSE_CMP_BRANCH to ALU_BRANCH, and AARCH64_FUSE_ALU_BRANCH to ALU_CBZ to make it clear what is being fused. gcc/ * config/aarch64/aarch64.c (thunderxt88_tunings): Use AARCH64_FUSE_ALU_BRANCH. (thunderx_tunings): Likewise. (tsv110_tunings): Use AARCH64_FUSE_ALU_BRANCH and AARCH64_FUSE_ALU_CBZ. (thunderx2t99_tunings): Likewise. (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_CMP_BRANCH. * config/aarch64/aarch64-fusion-pairs.def: Add ALU_CBZ fusion. From-SVN: r278966 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 29359ee3f5b..3d59aeab210 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2019-12-04 Wilco Dijkstra + + * config/aarch64/aarch64.c + (thunderxt88_tunings): Use AARCH64_FUSE_ALU_BRANCH. + (thunderx_tunings): Likewise. + (tsv110_tunings): Use AARCH64_FUSE_ALU_BRANCH and AARCH64_FUSE_ALU_CBZ. + (thunderx2t99_tunings): Likewise. + (aarch_macro_fusion_pair_p): Add support for AARCH64_FUSE_CMP_BRANCH. + * config/aarch64/aarch64-fusion-pairs.def: Add ALU_CBZ fusion. + 2019-12-04 Richard Biener * tree-ssa-sccvn.c (vn_reference_lookup_3): Properly guard diff --git a/gcc/config/aarch64/aarch64-fusion-pairs.def b/gcc/config/aarch64/aarch64-fusion-pairs.def index ce4bb92d5c9..051009b42b2 100644 --- a/gcc/config/aarch64/aarch64-fusion-pairs.def +++ b/gcc/config/aarch64/aarch64-fusion-pairs.def @@ -35,5 +35,6 @@ AARCH64_FUSION_PAIR ("adrp+ldr", ADRP_LDR) AARCH64_FUSION_PAIR ("cmp+branch", CMP_BRANCH) AARCH64_FUSION_PAIR ("aes+aesmc", AES_AESMC) AARCH64_FUSION_PAIR ("alu+branch", ALU_BRANCH) +AARCH64_FUSION_PAIR ("alu+cbz", ALU_CBZ) #undef AARCH64_FUSION_PAIR diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c0d49fb7cf0..a3b18b381e1 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -915,7 +915,7 @@ static const struct tune_params thunderxt88_tunings = SVE_NOT_IMPLEMENTED, /* sve_width */ 6, /* memmov_cost */ 2, /* issue_rate */ - AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */ + AARCH64_FUSE_ALU_BRANCH, /* fusible_ops */ "8", /* function_align. */ "8", /* jump_align. */ "8", /* loop_align. */ @@ -941,7 +941,7 @@ static const struct tune_params thunderx_tunings = SVE_NOT_IMPLEMENTED, /* sve_width */ 6, /* memmov_cost */ 2, /* issue_rate */ - AARCH64_FUSE_CMP_BRANCH, /* fusible_ops */ + AARCH64_FUSE_ALU_BRANCH, /* fusible_ops */ "8", /* function_align. */ "8", /* jump_align. */ "8", /* loop_align. */ @@ -968,8 +968,8 @@ static const struct tune_params tsv110_tunings = SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost */ 4, /* issue_rate */ - (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_CMP_BRANCH - | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ + (AARCH64_FUSE_AES_AESMC | AARCH64_FUSE_ALU_BRANCH + | AARCH64_FUSE_ALU_CBZ), /* fusible_ops */ "16", /* function_align. */ "4", /* jump_align. */ "8", /* loop_align. */ @@ -1103,8 +1103,8 @@ static const struct tune_params thunderx2t99_tunings = SVE_NOT_IMPLEMENTED, /* sve_width */ 4, /* memmov_cost. */ 4, /* issue_rate. */ - (AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_AES_AESMC - | AARCH64_FUSE_ALU_BRANCH), /* fusible_ops */ + (AARCH64_FUSE_ALU_BRANCH | AARCH64_FUSE_AES_AESMC + | AARCH64_FUSE_ALU_CBZ), /* fusible_ops */ "16", /* function_align. */ "8", /* jump_align. */ "16", /* loop_align. */ @@ -20396,7 +20396,16 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) } } + /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */ if (aarch64_fusion_enabled_p (AARCH64_FUSE_CMP_BRANCH) + && prev_set && curr_set && any_condjump_p (curr) + && GET_CODE (SET_SRC (prev_set)) == COMPARE + && SCALAR_INT_MODE_P (GET_MODE (XEXP (SET_SRC (prev_set), 0))) + && reg_referenced_p (SET_DEST (prev_set), PATTERN (curr))) + return true; + + /* Fuse flag-setting ALU instructions and conditional branch. */ + if (aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) && any_condjump_p (curr)) { unsigned int condreg1, condreg2; @@ -20420,9 +20429,10 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) } } + /* Fuse ALU instructions and CBZ/CBNZ. */ if (prev_set && curr_set - && aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_BRANCH) + && aarch64_fusion_enabled_p (AARCH64_FUSE_ALU_CBZ) && any_condjump_p (curr)) { /* We're trying to match: