From: Jacob Lifshay Date: Mon, 7 Aug 2023 23:04:00 +0000 (-0700) Subject: split out instructions from openpower/isa/fptrans.mdwn X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a4fcd46323321f4bd764331413d7b0ec07ce3215;p=openpower-isa.git split out instructions from openpower/isa/fptrans.mdwn --- diff --git a/openpower/isa/fptrans.mdwn b/openpower/isa/fptrans.mdwn index 9060c79f..78e76b41 100644 --- a/openpower/isa/fptrans.mdwn +++ b/openpower/isa/fptrans.mdwn @@ -2,1585 +2,172 @@ -# [DRAFT] Floating ATAN2 Single +[[!inline pagenames="openpower/isa/fptrans/fatan2s" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fatan2" raw="yes"]] -* fatan2s FRT,FRA,FRB (Rc=0) -* fatan2s. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fatan2pis" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fatan2pi" raw="yes"]] - FRT <- DOUBLE(bfp32_ATAN2(SINGLE(FRA), SINGLE(FRB))) +[[!inline pagenames="openpower/isa/fptrans/fpows" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fpow" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fpowns" raw="yes"]] -# [DRAFT] Floating ATAN2 +[[!inline pagenames="openpower/isa/fptrans/fpown" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fpowrs" raw="yes"]] -* fatan2 FRT,FRA,FRB (Rc=0) -* fatan2. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fpowr" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/frootns" raw="yes"]] - FRT <- bfp64_ATAN2(FRA, FRB) +[[!inline pagenames="openpower/isa/fptrans/frootn" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fhypots" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fhypot" raw="yes"]] -# [DRAFT] Floating ATAN2PI Single +[[!inline pagenames="openpower/isa/fptrans/frsqrts" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/frsqrt" raw="yes"]] -* fatan2pis FRT,FRA,FRB (Rc=0) -* fatan2pis. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fcbrts" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fcbrt" raw="yes"]] - FRT <- DOUBLE(bfp32_ATAN2PI(SINGLE(FRA), SINGLE(FRB))) +[[!inline pagenames="openpower/isa/fptrans/frecips" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/frecip" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fexp2m1s" raw="yes"]] -# [DRAFT] Floating ATAN2PI +[[!inline pagenames="openpower/isa/fptrans/fexp2m1" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/flog2p1s" raw="yes"]] -* fatan2pi FRT,FRA,FRB (Rc=0) -* fatan2pi. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/flog2p1" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fexp2s" raw="yes"]] - FRT <- bfp64_ATAN2PI(FRA, FRB) +[[!inline pagenames="openpower/isa/fptrans/fexp2" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/flog2s" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/flog2" raw="yes"]] -# [DRAFT] Floating POW Single +[[!inline pagenames="openpower/isa/fptrans/fexpm1s" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fexpm1" raw="yes"]] -* fpows FRT,FRA,FRB (Rc=0) -* fpows. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/flogp1s" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/flogp1" raw="yes"]] - FRT <- DOUBLE(bfp32_POW(SINGLE(FRA), SINGLE(FRB))) +[[!inline pagenames="openpower/isa/fptrans/fexps" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fexp" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/flogs" raw="yes"]] -# [DRAFT] Floating POW +[[!inline pagenames="openpower/isa/fptrans/flog" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fexp10m1s" raw="yes"]] -* fpow FRT,FRA,FRB (Rc=0) -* fpow. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fexp10m1" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/flog10p1s" raw="yes"]] - FRT <- bfp64_POW(FRA, FRB) +[[!inline pagenames="openpower/isa/fptrans/flog10p1" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fexp10s" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fexp10" raw="yes"]] -# [DRAFT] Floating POWN Single +[[!inline pagenames="openpower/isa/fptrans/flog10s" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/flog10" raw="yes"]] -* fpowns FRT,FRA,RB (Rc=0) -* fpowns. FRT,FRA,RB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fsins" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fsin" raw="yes"]] - FRT <- DOUBLE(bfp32_POWN(SINGLE(FRA), RB)) +[[!inline pagenames="openpower/isa/fptrans/fcoss" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fcos" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/ftans" raw="yes"]] -# [DRAFT] Floating POWN +[[!inline pagenames="openpower/isa/fptrans/ftan" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fasins" raw="yes"]] -* fpown FRT,FRA,RB (Rc=0) -* fpown. FRT,FRA,RB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fasin" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/facoss" raw="yes"]] - FRT <- bfp64_POWN(FRA, RB) +[[!inline pagenames="openpower/isa/fptrans/facos" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fatans" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fatan" raw="yes"]] -# [DRAFT] Floating POWR Single +[[!inline pagenames="openpower/isa/fptrans/fsinpis" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fsinpi" raw="yes"]] -* fpowrs FRT,FRA,FRB (Rc=0) -* fpowrs. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fcospis" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fcospi" raw="yes"]] - FRT <- DOUBLE(bfp32_POWR(SINGLE(FRA), SINGLE(FRB))) +[[!inline pagenames="openpower/isa/fptrans/ftanpis" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/ftanpi" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fasinpis" raw="yes"]] -# [DRAFT] Floating POWR +[[!inline pagenames="openpower/isa/fptrans/fasinpi" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/facospis" raw="yes"]] -* fpowr FRT,FRA,FRB (Rc=0) -* fpowr. FRT,FRA,FRB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/facospi" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fatanpis" raw="yes"]] - FRT <- bfp64_POWR(FRA, FRB) +[[!inline pagenames="openpower/isa/fptrans/fatanpi" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fsinhs" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fsinh" raw="yes"]] -# [DRAFT] Floating ROOTN Single +[[!inline pagenames="openpower/isa/fptrans/fcoshs" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fcosh" raw="yes"]] -* frootns FRT,FRA,RB (Rc=0) -* frootns. FRT,FRA,RB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/ftanhs" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/ftanh" raw="yes"]] - FRT <- DOUBLE(bfp32_ROOTN(SINGLE(FRA), RB)) +[[!inline pagenames="openpower/isa/fptrans/fasinhs" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fasinh" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) +[[!inline pagenames="openpower/isa/fptrans/facoshs" raw="yes"]] -# [DRAFT] Floating ROOTN +[[!inline pagenames="openpower/isa/fptrans/facosh" raw="yes"]] -X-Form +[[!inline pagenames="openpower/isa/fptrans/fatanhs" raw="yes"]] -* frootn FRT,FRA,RB (Rc=0) -* frootn. FRT,FRA,RB (Rc=1) +[[!inline pagenames="openpower/isa/fptrans/fatanh" raw="yes"]] -Pseudo-code: +[[!inline pagenames="openpower/isa/fptrans/fminmax" raw="yes"]] - FRT <- bfp64_ROOTN(FRA, RB) +[[!inline pagenames="openpower/isa/fptrans/fmods" raw="yes"]] -Special Registers Altered: +[[!inline pagenames="openpower/isa/fptrans/fmod" raw="yes"]] - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating HYPOT Single - -X-Form - -* fhypots FRT,FRA,FRB (Rc=0) -* fhypots. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_HYPOT(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating HYPOT - -X-Form - -* fhypot FRT,FRA,FRB (Rc=0) -* fhypot. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_HYPOT(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating RSQRT Single - -X-Form - -* frsqrts FRT,FRB (Rc=0) -* frsqrts. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_RSQRT(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating RSQRT - -X-Form - -* frsqrt FRT,FRB (Rc=0) -* frsqrt. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_RSQRT(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating CBRT Single - -X-Form - -* fcbrts FRT,FRB (Rc=0) -* fcbrts. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_CBRT(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating CBRT - -X-Form - -* fcbrt FRT,FRB (Rc=0) -* fcbrt. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_CBRT(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating RECIP Single - -X-Form - -* frecips FRT,FRB (Rc=0) -* frecips. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_RECIP(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating RECIP - -X-Form - -* frecip FRT,FRB (Rc=0) -* frecip. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_RECIP(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP2M1 Single - -X-Form - -* fexp2m1s FRT,FRB (Rc=0) -* fexp2m1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXP2M1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP2M1 - -X-Form - -* fexp2m1 FRT,FRB (Rc=0) -* fexp2m1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXP2M1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG2P1 Single - -X-Form - -* flog2p1s FRT,FRB (Rc=0) -* flog2p1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOG2P1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG2P1 - -X-Form - -* flog2p1 FRT,FRB (Rc=0) -* flog2p1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOG2P1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP2 Single - -X-Form - -* fexp2s FRT,FRB (Rc=0) -* fexp2s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXP2(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP2 - -X-Form - -* fexp2 FRT,FRB (Rc=0) -* fexp2. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXP2(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG2 Single - -X-Form - -* flog2s FRT,FRB (Rc=0) -* flog2s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOG2(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG2 - -X-Form - -* flog2 FRT,FRB (Rc=0) -* flog2. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOG2(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXPM1 Single - -X-Form - -* fexpm1s FRT,FRB (Rc=0) -* fexpm1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXPM1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXPM1 - -X-Form - -* fexpm1 FRT,FRB (Rc=0) -* fexpm1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXPM1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOGP1 Single - -X-Form - -* flogp1s FRT,FRB (Rc=0) -* flogp1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOGP1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOGP1 - -X-Form - -* flogp1 FRT,FRB (Rc=0) -* flogp1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOGP1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP Single - -X-Form - -* fexps FRT,FRB (Rc=0) -* fexps. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXP(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP - -X-Form - -* fexp FRT,FRB (Rc=0) -* fexp. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXP(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG Single - -X-Form - -* flogs FRT,FRB (Rc=0) -* flogs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOG(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG - -X-Form - -* flog FRT,FRB (Rc=0) -* flog. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOG(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP10M1 Single - -X-Form - -* fexp10m1s FRT,FRB (Rc=0) -* fexp10m1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXP10M1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP10M1 - -X-Form - -* fexp10m1 FRT,FRB (Rc=0) -* fexp10m1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXP10M1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG10P1 Single - -X-Form - -* flog10p1s FRT,FRB (Rc=0) -* flog10p1s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOG10P1(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG10P1 - -X-Form - -* flog10p1 FRT,FRB (Rc=0) -* flog10p1. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOG10P1(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP10 Single - -X-Form - -* fexp10s FRT,FRB (Rc=0) -* fexp10s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_EXP10(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating EXP10 - -X-Form - -* fexp10 FRT,FRB (Rc=0) -* fexp10. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_EXP10(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG10 Single - -X-Form - -* flog10s FRT,FRB (Rc=0) -* flog10s. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_LOG10(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating LOG10 - -X-Form - -* flog10 FRT,FRB (Rc=0) -* flog10. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_LOG10(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SIN Single - -X-Form - -* fsins FRT,FRB (Rc=0) -* fsins. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_SIN(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SIN - -X-Form - -* fsin FRT,FRB (Rc=0) -* fsin. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_SIN(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COS Single - -X-Form - -* fcoss FRT,FRB (Rc=0) -* fcoss. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_COS(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COS - -X-Form - -* fcos FRT,FRB (Rc=0) -* fcos. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_COS(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TAN Single - -X-Form - -* ftans FRT,FRB (Rc=0) -* ftans. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_TAN(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TAN - -X-Form - -* ftan FRT,FRB (Rc=0) -* ftan. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_TAN(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASIN Single - -X-Form - -* fasins FRT,FRB (Rc=0) -* fasins. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ASIN(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASIN - -X-Form - -* fasin FRT,FRB (Rc=0) -* fasin. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ASIN(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOS Single - -X-Form - -* facoss FRT,FRB (Rc=0) -* facoss. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ACOS(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOS - -X-Form - -* facos FRT,FRB (Rc=0) -* facos. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ACOS(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATAN Single - -X-Form - -* fatans FRT,FRB (Rc=0) -* fatans. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ATAN(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATAN - -X-Form - -* fatan FRT,FRB (Rc=0) -* fatan. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ATAN(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SINPI Single - -X-Form - -* fsinpis FRT,FRB (Rc=0) -* fsinpis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_SINPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SINPI - -X-Form - -* fsinpi FRT,FRB (Rc=0) -* fsinpi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_SINPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COSPI Single - -X-Form - -* fcospis FRT,FRB (Rc=0) -* fcospis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_COSPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COSPI - -X-Form - -* fcospi FRT,FRB (Rc=0) -* fcospi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_COSPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TANPI Single - -X-Form - -* ftanpis FRT,FRB (Rc=0) -* ftanpis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_TANPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TANPI - -X-Form - -* ftanpi FRT,FRB (Rc=0) -* ftanpi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_TANPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASINPI Single - -X-Form - -* fasinpis FRT,FRB (Rc=0) -* fasinpis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ASINPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASINPI - -X-Form - -* fasinpi FRT,FRB (Rc=0) -* fasinpi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ASINPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOSPI Single - -X-Form - -* facospis FRT,FRB (Rc=0) -* facospis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ACOSPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOSPI - -X-Form - -* facospi FRT,FRB (Rc=0) -* facospi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ACOSPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATANPI Single - -X-Form - -* fatanpis FRT,FRB (Rc=0) -* fatanpis. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ATANPI(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATANPI - -X-Form - -* fatanpi FRT,FRB (Rc=0) -* fatanpi. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ATANPI(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SINH Single - -X-Form - -* fsinhs FRT,FRB (Rc=0) -* fsinhs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_SINH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating SINH - -X-Form - -* fsinh FRT,FRB (Rc=0) -* fsinh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_SINH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COSH Single - -X-Form - -* fcoshs FRT,FRB (Rc=0) -* fcoshs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_COSH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating COSH - -X-Form - -* fcosh FRT,FRB (Rc=0) -* fcosh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_COSH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TANH Single - -X-Form - -* ftanhs FRT,FRB (Rc=0) -* ftanhs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_TANH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating TANH - -X-Form - -* ftanh FRT,FRB (Rc=0) -* ftanh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_TANH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASINH Single - -X-Form - -* fasinhs FRT,FRB (Rc=0) -* fasinhs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ASINH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ASINH - -X-Form - -* fasinh FRT,FRB (Rc=0) -* fasinh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ASINH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOSH Single - -X-Form - -* facoshs FRT,FRB (Rc=0) -* facoshs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ACOSH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ACOSH - -X-Form - -* facosh FRT,FRB (Rc=0) -* facosh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ACOSH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATANH Single - -X-Form - -* fatanhs FRT,FRB (Rc=0) -* fatanhs. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_ATANH(SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating ATANH - -X-Form - -* fatanh FRT,FRB (Rc=0) -* fatanh. FRT,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_ATANH(FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating Minimum/Maximum - -MM-Form - -* fminmax FRT,FRA,FRB,FMM (Rc=0) -* fminmax. FRT,FRA,FRB,FMM (Rc=1) - -Pseudo-code: - - result <- [0] * 64 - a <- (FRA) - b <- (FRB) - abs_a <- 0b0 || a[1:63] - abs_b <- 0b0 || b[1:63] - a_is_nan <- abs_a >u 0x7FF0_0000_0000_0000 - a_is_snan <- a_is_nan & (a[12] = 0) - b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000 - b_is_snan <- b_is_nan & (b[12] = 0) - any_snan <- a_is_snan | b_is_snan - a_quieted <- a - a_quieted[12] <- 1 - b_quieted <- b - b_quieted[12] <- 1 - if a_is_nan | b_is_nan then - if FMM[2:3] = 0b00 then # min/maxnum08 - if a_is_snan then result <- a_quieted - else if b_is_snan then result <- b_quieted - else if a_is_nan & b_is_nan then result <- a_quieted - else if a_is_nan then result <- b - else result <- a - if FMM[2:3] = 0b01 then # min/max19 - if a_is_nan then result <- a_quieted - else result <- b_quieted - if FMM[2:3] = 0b10 then # min/maxnum19 - if a_is_nan & b_is_nan then result <- a_quieted - else if a_is_nan then result <- b - else result <- a - if FMM[2:3] = 0b11 then # min/maxc - result <- b - else - cmp_l <- a - cmp_r <- b - if FMM[1] then # min/maxmag - if abs_a != abs_b then - cmp_l <- abs_a - cmp_r <- abs_b - if FMM[2:3] = 0b11 then # min/maxc - if abs_a = 0 then cmp_l[0:63] <- 0 - if abs_b = 0 then cmp_r[0:63] <- 0 - if FMM[0] then # max - # swap cmp_* so comparison goes the other way - cmp_l, cmp_r <- cmp_r, cmp_l - if cmp_l[0] = 1 then - if cmp_r[0] = 0 then result <- a - else if cmp_l >u cmp_r then - # IEEE 754 is sign-magnitude, - # so bigger magnitude negative is smaller - result <- a - else result <- b - else if cmp_r[0] = 1 then result <- b - else if cmp_l u 0x7FF0_0000_0000_0000 + a_is_snan <- a_is_nan & (a[12] = 0) + b_is_nan <- abs_b >u 0x7FF0_0000_0000_0000 + b_is_snan <- b_is_nan & (b[12] = 0) + any_snan <- a_is_snan | b_is_snan + a_quieted <- a + a_quieted[12] <- 1 + b_quieted <- b + b_quieted[12] <- 1 + if a_is_nan | b_is_nan then + if FMM[2:3] = 0b00 then # min/maxnum08 + if a_is_snan then result <- a_quieted + else if b_is_snan then result <- b_quieted + else if a_is_nan & b_is_nan then result <- a_quieted + else if a_is_nan then result <- b + else result <- a + if FMM[2:3] = 0b01 then # min/max19 + if a_is_nan then result <- a_quieted + else result <- b_quieted + if FMM[2:3] = 0b10 then # min/maxnum19 + if a_is_nan & b_is_nan then result <- a_quieted + else if a_is_nan then result <- b + else result <- a + if FMM[2:3] = 0b11 then # min/maxc + result <- b + else + cmp_l <- a + cmp_r <- b + if FMM[1] then # min/maxmag + if abs_a != abs_b then + cmp_l <- abs_a + cmp_r <- abs_b + if FMM[2:3] = 0b11 then # min/maxc + if abs_a = 0 then cmp_l[0:63] <- 0 + if abs_b = 0 then cmp_r[0:63] <- 0 + if FMM[0] then # max + # swap cmp_* so comparison goes the other way + cmp_l, cmp_r <- cmp_r, cmp_l + if cmp_l[0] = 1 then + if cmp_r[0] = 0 then result <- a + else if cmp_l >u cmp_r then + # IEEE 754 is sign-magnitude, + # so bigger magnitude negative is smaller + result <- a + else result <- b + else if cmp_r[0] = 1 then result <- b + else if cmp_l