From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Apr 2020 17:36:07 +0000 (-0700)
Subject: ecp5: (* abc9_flop *) gated behind YOSYS
X-Git-Tag: working-ls180~549^2~50
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a52f779ecae79be5ea79bd27f04837e7031f8415;p=yosys.git

ecp5: (* abc9_flop *) gated behind YOSYS
---

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 69685683f..563592218 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -294,7 +294,9 @@ endmodule
 
 // ---------------------------------------
 
+`ifdef YOSYS
 (* abc9_flop=(SRMODE != "ASYNC"), lib_whitebox=(SRMODE != "ASYNC") *)
+`endif
 module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";