From: Luke Kenneth Casson Leighton Date: Tue, 16 Oct 2018 00:39:42 +0000 (+0100) Subject: add reshaping section X-Git-Tag: convert-csv-opcode-to-binary~4931 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a535e69524cb91c9556c7f961c30772ab5b74cb4;p=libreriscv.git add reshaping section --- diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index b46d937f1..22c22febb 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -428,10 +428,10 @@ up to 3 registers: | ------ | ------ | ------ | -- | ------- | -- | ------- | -- | ------- | | shape2 | shape1 | shape0 | 0 | regidx2 | 0 | regidx1 | 0 | regidx0 | -regidx0-2 refer not to the Registe CSR CAM entry but to the underlying +regidx0-2 refer not to the Register CSR CAM entry but to the underlying *real* register (see regidx, the value) and consequently is 7-bits wide. shape0-2 refers to one of three SHAPE CSRs. A value of 0x3 is reserved. -Bits 7, 15, 23, 30 and 31 are reserved, and must be set to zero. +Bits 7, 15, 23, 30 and 31 are also reserved, and must be set to zero. ## SHAPE 1D/2D/3D vector-matrix remapping CSRs