From: lkcl <lkcl@web>
Date: Fri, 27 May 2022 09:03:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2068
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a541570a3a4d1b8461c7739f66cedcede5815fe9;p=libreriscv.git

---

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 754b510da..33743af8f 100644
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,6 +11,14 @@ That said, there are a few exceptional places where these rules get
 bent, and others where the rules take some explaining,
 and this page tracks them.
 
+*(An experiment was attempted to modify LD-immediate instructions
+to include a
+third RC register i.e. reinterpret the normal
+v3.0 32-bit instruction as a
+different encoding if SVP64-prefixed: it did not go well.
+The complexity that resulted
+in the decode phase was too great)*
+
 # CR weird instructions
 
 [[sv/int_cr_predication]] is by far the biggest violator of the SVP64