From: lkcl <lkcl@web>
Date: Mon, 3 Apr 2023 12:34:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~158
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a54986d296c381e45f9990e7f1c76da4a07970cb;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index ec9c8ba20..21d81e71b 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -1,6 +1,89 @@
 # RFC ls010 SVP64 Zero-Overhead Loop Prefix Subsystem
+**URLs**:
 
-TODO template from other RFCs
+* <https://libre-soc.org/openpower/sv/>
+* <https://libre-soc.org/openpower/sv/rfc/ls010/>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=1045>
+* <https://git.openpower.foundation/isa/PowerISA/issues/64>
+
+**Severity**: Major
+
+**Status**: New
+
+**Date**: 04 Apr 2023 v1
+
+**Target**: v3.2B
+
+**Source**: v3.0B
+
+**Books and Section affected**:
+
+```
+    New Book: new Zero-Overhead-Loop
+    New Appendix, Zero-Overhead-Loop
+```
+
+**Summary**
+
+```
+    Adds a Zero-Overhead-Loop Subsystem based on the Cray True-Scalable Vector concept
+    in a RISC-paradigm fashion.  Total instructions added is six, plus Prefix format.
+```
+
+**Submitter**: Luke Leighton (Libre-SOC)
+
+**Requester**: Libre-SOC
+
+**Impact on processor**:
+
+```
+    Addition of new "Zero-Overhead-Loop-Control" DSP-style Vector-style
+    subsystem that in simple low-end (Embedded) systems may be minimalistically
+    and easily be implemented by inserting a new fully-independent Pipeline Stage
+    in between Decode and Issue, with very little disruption, and in higher
+    performance pre-existing Multi-Issue Out-of-Order systems seamlessly fits likewise
+    to significantly boost performance.
+```
+
+**Impact on software**:
+
+```
+    Requires support for new instructions in assembler, debuggers, and related tools.
+    Dramatically reduces instructions. Requires introduction of term "High-Level Assembler"
+```
+
+**Keywords**:
+
+```
+    Cray Supercomputing, Vectorisation, Zero-Overhead-Loop-Control (ZOLC),
+    True-Scalable Vectors, Multi-Issue Out-of-Order, Sequential Programming Model,
+    Digital Signal Processing (DSP), High-level Assembler
+```
+
+**Motivation**
+
+SIMD is getting out of control and damaging the reputation of mainstream
+general-purpose ISAs that offer it.  A solution from 50 years ago exists
+in the form of Cray-Style True-Scalable Vectors.  However the usual way that
+True-Scalable Vector ISAs are done *also* adds more instructions and
+complexifies the ISA.  Simple-V takes a step back to a simpler era in
+computing from half a century ago: the Zilog Z80 CPIR and LDIR instructions,
+and the 8086 REP instruction, and brings them forward to Modern-day Computing.
+The result is a huge reduction in programming complexity, and a strong
+base to project the Power ISA back to the most powerful Supercomputing ISA
+for at least the next two decades.
+
+**Notes and Observations**:
+
+1. TODO
+
+**Changes**
+
+Add the following entries to:
+
+* A new "Vector Looping" Book
+* New Vector-Looping Chapters
+* New Vector-Looping Appendices
 
 [[!tag opf_rfc]]