From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 8 May 2020 21:29:55 +0000 (+0100)
Subject: send address to memory only for one cycle and acknowledge LD immediately
X-Git-Tag: div_pipeline~1327
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a54adcb65bad37b398b11e33a824c7d08c5fe509;p=soc.git

send address to memory only for one cycle and acknowledge LD immediately
in test-L0CacheBuffer
---

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 204d4ec4..5dc6daae 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -272,11 +272,10 @@ class L0CacheBuffer(Elaboratable):
         # if now in "LD" mode: wait for addr_ok, then send the address out
         # to memory, acknowledge address, and send out LD data
         with m.If(ld_active.q):
-            with m.If(ldport.addr.ok):
+            with m.If(ldport.addr.ok & adrok_l.qn):
                 comb += rdport.addr.eq(ldport.addr.data) # addr ok, send thru
-                with m.If(adrok_l.qn):
-                    comb += ldport.addr_ok_o.eq(1) # acknowledge addr ok
-                    sync += adrok_l.s.eq(1)       # and pull "ack" latch
+                comb += ldport.addr_ok_o.eq(1) # acknowledge addr ok
+                sync += adrok_l.s.eq(1)       # and pull "ack" latch
 
         # if now in "ST" mode: likewise do the same but with "ST"
         # to memory, acknowledge address, and send out LD data