From: Florent Kermarrec Date: Wed, 30 Oct 2019 15:33:40 +0000 (+0100) Subject: targets: use type="io" instead of io_region=True X-Git-Tag: 24jan2021_ls180~891 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a54b80b9b4eaa6defca99b0749da8426535bbb62;p=litex.git targets: use type="io" instead of io_region=True --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index d8b148a4..8696fe4b 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -86,7 +86,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 9d2ef599..e922e676 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -78,7 +78,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 17d6a108..649f1678 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -80,7 +80,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index ba3accd4..a48c86c1 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -117,7 +117,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 9bfa6739..57ba7869 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 742e3342..bbb7b416 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -84,7 +84,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 06b656b1..74313045 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -83,7 +83,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index b615a669..dea752dc 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -44,7 +44,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index f2d9275f..965f82af 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -118,7 +118,7 @@ class EthernetSoC(BaseSoC): self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, io_region=True) + self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac")