From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 10:46:40 +0000 (+0100)
Subject: set fraction width to zero
X-Git-Tag: ls180-24jan2020~771
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5617e1a74eef51a933cc1b34dafa7215399ae3e;p=ieee754fpu.git

set fraction width to zero
---

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 63f30e73..1b3a0b33 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -163,7 +163,7 @@ class FPDIVMuxInOut(ReservationStations):
         # also: round up to nearest radix
         fmt.m_width = roundup(fmt.m_width + 4, log2_radix)
 
-        cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)
+        cfg = DivPipeCoreConfig(fmt.m_width, 0*fmt.fraction_width, log2_radix)
 
         self.pspec.fpformat = fmt
         self.pspec.log2_radix = log2_radix