From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 18:28:13 +0000 (-0800)
Subject: Disable RAM16X1D test
X-Git-Tag: working-ls180~921^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5764a12365073768edb822e893aa9c0a957e585;p=yosys.git

Disable RAM16X1D test
---

diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index a2ede75a5..6c9d1eae1 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -1,20 +1,20 @@
-read_verilog ../common/lutram.v
-hierarchy -top lutram_1w1r -chparam A_WIDTH 4
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd lutram_1w1r
-select -assert-count 1 t:BUFG
-select -assert-count 8 t:FDRE
-select -assert-count 8 t:RAM16X1D
-select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
+#read_verilog ../common/lutram.v
+#hierarchy -top lutram_1w1r -chparam A_WIDTH 4
+#proc
+#memory -nomap
+#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+#memory
+#opt -full
+#
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+#
+#design -load postopt
+#cd lutram_1w1r
+#select -assert-count 1 t:BUFG
+#select -assert-count 8 t:FDRE
+#select -assert-count 8 t:RAM16X1D
+#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
 
 
 design -reset