From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:08:42 +0000 (+0200)
Subject: split latches into separate checks
X-Git-Tag: working-ls180~988^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5844e3ceb76152d1e87ad8fdf1c71553238ef64;p=yosys.git

split latches into separate checks
---

diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v
index 9dc43e4c2..adb5d5319 100644
--- a/tests/anlogic/latches.v
+++ b/tests/anlogic/latches.v
@@ -22,37 +22,3 @@ module latchsr
 		else if ( en )
 			q <= d;
 endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys
index b5e52cf16..ae9e15ff8 100644
--- a/tests/anlogic/latches.ys
+++ b/tests/anlogic/latches.ys
@@ -2,15 +2,32 @@ read_verilog latches.v
 design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
-flatten
+hierarchy -top latchp
+# Can't run any sort of equivalence check because latches are blown to LUTs
 synth_anlogic
-equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchn
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_anlogic
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+
+select -assert-none t:AL_MAP_LUT3 %% t:* %D
+
 
 design -load read
+proc
+hierarchy -top latchsr
+# Can't run any sort of equivalence check because latches are blown to LUTs
 synth_anlogic
-cd top
-select -assert-count 2 t:AL_MAP_LUT3
+cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:AL_MAP_LUT5
-select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D
+
+select -assert-none t:AL_MAP_LUT5 %% t:* %D