From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 15 Jan 2015 11:53:12 +0000 (+0100)
Subject: Fixed handling of "input foo; reg [0:0] foo;"
X-Git-Tag: yosys-0.5~107
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a588a4a5c95d14e62678c98b14af139903980be3;p=yosys.git

Fixed handling of "input foo; reg [0:0] foo;"
---

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 5ab778e66..552fc04bc 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -186,6 +186,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					AstNode *first_node = this_wire_scope[node->str];
 					if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
 						goto wires_are_compatible;
+					if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
+						AstNode *r = node->children[0];
+						if (r->range_valid && r->range_left == 0 && r->range_right == 0) {
+							delete r;
+							node->children.pop_back();
+						}
+					}
 					if (first_node->children.size() != node->children.size())
 						goto wires_are_incompatible;
 					for (size_t j = 0; j < node->children.size(); j++) {