From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 1 Jan 2020 02:40:11 +0000 (-0800)
Subject: Fix warnings
X-Git-Tag: working-ls180~891^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a59016b146e91311324bc87f9a9437d7ff31d9f2;p=yosys.git

Fix warnings
---

diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys
index 9891b77d6..b8c3eb941 100644
--- a/tests/arch/ice40/mul.ys
+++ b/tests/arch/ice40/mul.ys
@@ -1,6 +1,6 @@
 read_verilog ../common/mul.v
 hierarchy -top top
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16
diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v
index 0a0f41f37..c4c677c1e 100644
--- a/tests/arch/ice40/rom.v
+++ b/tests/arch/ice40/rom.v
@@ -2,7 +2,7 @@
 Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
 */
 module top(data, addr);
-output [3:0] data;
+output reg [3:0] data;
 input [4:0] addr;
 always @(addr) begin
 case (addr)