From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 24 May 2020 19:44:12 +0000 (-0300)
Subject: Rename the internal DFF of latchregisters to avoid conflict
X-Git-Tag: div_pipeline~864
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5968ecf27c0be3b357342889aaa8e48c1a519cb;p=soc.git

Rename the internal DFF of latchregisters to avoid conflict
---

diff --git a/src/soc/experiment/compalu.py b/src/soc/experiment/compalu.py
index 0cc26515..52e21f7b 100644
--- a/src/soc/experiment/compalu.py
+++ b/src/soc/experiment/compalu.py
@@ -98,11 +98,11 @@ class ComputationUnitNoDelay(Elaboratable):
 
         # create a latch/register for the operand
         oper_r = CompALUOpSubset()
-        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True)  # Dest register
-        latchregister(m, self.alu.o, data_r, req_l.q, "data_r")
+        latchregister(m, self.alu.o, data_r, req_l.q, "data_l")
 
         # pass the operation to the ALU
         m.d.comb += self.alu.op.eq(oper_r)
diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 75df2153..10d3ae79 100644
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -205,14 +205,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
         # create a latch/register for the operand
         oper_r = self.opsubsetkls()
-        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, "oper_l")
 
         # and for each output from the ALU
         drl = []
         for i in range(self.n_dst):
             name = "data_r%d" % i
             data_r = Signal(self.cu._get_srcwid(i), name=name, reset_less=True)
-            latchregister(m, self.get_out(i), data_r, req_l.q[i], name)
+            latchregister(m, self.get_out(i), data_r, req_l.q[i], name + "_l")
             drl.append(data_r)
 
         # pass the operation to the ALU
diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index e4f51b60..f5ee73b0 100644
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -257,7 +257,7 @@ class LDSTCompUnit(Elaboratable):
 
         # create a latch/register for the operand
         oper_r = CompALUOpSubset()  # Dest register
-        latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 
         # and one for the output from the ALU
         data_r = Signal(self.rwid, reset_less=True)  # Dest register
@@ -288,8 +288,8 @@ class LDSTCompUnit(Elaboratable):
                                               self.src2_i))
 
         # create a latch/register for src1/src2 (include immediate select)
-        latchregister(m, self.src1_i, self.alu.a, src_l.q, name="src1_r")
-        latchregister(m, self.src2_i, src2_r, src_l.q, name="src2_r")
+        latchregister(m, self.src1_i, self.alu.a, src_l.q, name="src1_l")
+        latchregister(m, self.src2_i, src2_r, src_l.q, name="src2_l")
         latchregister(m, src2_or_imm, self.alu.b, src_sel, name="imm_r")
 
         # decode bits of operand (latched)
diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 6988c6f3..a0ee965d 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -336,7 +336,7 @@ class LDSTCompUnit(Elaboratable):
 
         # create a latch/register for the operand
         oper_r = CompLDSTOpSubset()  # Dest register
-        latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_r")
+        latchregister(m, self.oper_i, oper_r, self.issue_i, name="oper_l")
 
         # and for LD
         ldd_r = Signal(self.rwid, reset_less=True)  # Dest register
@@ -347,7 +347,7 @@ class LDSTCompUnit(Elaboratable):
         for i in range(self.n_src):
             name = "src_r%d" % i
             src_r = Signal(self.rwid, name=name, reset_less=True)
-            latchregister(m, self.src_i[i], src_r, src_l.q[i], name)
+            latchregister(m, self.src_i[i], src_r, src_l.q[i], name + '_l')
             srl.append(src_r)
 
         # and one for the output from the ADD (for the EA)
diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index ae26656b..09f8c1b6 100644
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -260,8 +260,8 @@ class L0CacheBuffer(Elaboratable):
         ld_idx = Signal(nbits, reset_less=False)
         st_idx = Signal(nbits, reset_less=False)
         # use these because of the sync-and-comb pass-through capability
-        latchregister(m, ldpick.o, ld_idx, idx_l.qn, name="ld_idx")
-        latchregister(m, stpick.o, st_idx, idx_l.qn, name="st_idx")
+        latchregister(m, ldpick.o, ld_idx, idx_l.qn, name="ld_idx_l")
+        latchregister(m, stpick.o, st_idx, idx_l.qn, name="st_idx_l")
 
         # convenience variables to reference the "picked" port
         ldport = self.dports[ld_idx].pi