From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 13 Nov 2020 18:02:05 +0000 (+0000)
Subject: increase chip size by 100, make chipSize closer to ring
X-Git-Tag: partial-core-ls180-gdsii~10
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a598fe04e8c948663fb4de3dd597c65f9a97f7af;p=soclayout.git

increase chip size by 100, make chipSize closer to ring
---

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index a7360d5..51cbf0e 100644
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -134,7 +134,7 @@ def scriptMain (**kw):
     """The mandatory function to be called by Coriolis CGT/Unicorn."""
     global af
     rvalue = True
-    sz = 25000 # core size
+    sz = 25100 # core size
     try:
         helpers.setTraceLevel(550)
         usePadsPosition = True
@@ -161,7 +161,7 @@ def scriptMain (**kw):
         ls180Conf.chipConf.name = 'chip'
         ls180Conf.chipConf.ioPadGauge = 'niolib'
         ls180Conf.coreSize = (l(sz), l(sz))
-        ls180Conf.chipSize = (l(sz+3500), l(sz+3500))
+        ls180Conf.chipSize = (l(sz+3430), l(sz+3430))
         ls180ToChip = CoreToChip(ls180Conf)
         ls180ToChip.buildChip()
         chipBuilder = Chip(ls180Conf)