From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 05:39:47 +0000 (-0700)
Subject: SB_MAC16 ffCD to not pack same as ffO
X-Git-Tag: working-ls180~1039^2~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a59f80834f7f8ecf02ed0c608dce1a237a874d34;p=yosys.git

SB_MAC16 ffCD to not pack same as ffO
---

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 35db22807..09fd8406d 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -188,7 +188,7 @@ match add
 	select nusers(port(add, AB)) == 2
 	index <SigBit> port(add, AB)[0] === sigH[0]
 	filter GetSize(port(add, AB)) <= GetSize(sigH)
-	filter port(add, AB) ==  sigH.extract(0, GetSize(port(add, AB)))
+	filter port(add, AB) == sigH.extract(0, GetSize(port(add, AB)))
 	filter nusers(sigH.extract_end(GetSize(port(add, AB)))) <= 1
 	set addAB AB
 	optional
@@ -280,7 +280,7 @@ code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_p
 endcode
 
 code argQ ffCD ffCDholdmux ffCDholdpol ffCDrstpol sigCD clock clock_pol
-	if (!sigCD.empty() &&
+	if (!sigCD.empty() && sigCD != sigO &&
 			(mul->type != \SB_MAC16 || (!param(mul, \C_REG).as_bool() && !param(mul, \D_REG).as_bool()))) {
 		argQ = sigCD;
 		subpattern(in_dffe);