From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 00:53:20 +0000 (-0700)
Subject: Merge branch 'master' into eddie/abc_to_abc9
X-Git-Tag: working-ls180~1002^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5ac33f230b5dd20273f6636e5b573ef0478b8f9;p=yosys.git

Merge branch 'master' into eddie/abc_to_abc9
---

a5ac33f230b5dd20273f6636e5b573ef0478b8f9
diff --cc passes/techmap/abc9.cc
index 1ebdaa29e,8932e860a..27106cc5d
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@@ -334,27 -334,32 +334,31 @@@ void abc9_module(RTLIL::Design *design
  		log_abort();
  
  	//if (script_file.empty() && !delay_target.empty())
 -	//	for (size_t pos = abc_script.find("dretime;"); pos != std::string::npos; pos = abc_script.find("dretime;", pos+1))
 -	//		abc_script = abc_script.substr(0, pos) + "dretime; retime -o {D};" + abc_script.substr(pos+8);
 +	//	for (size_t pos = abc9_script.find("dretime;"); pos != std::string::npos; pos = abc9_script.find("dretime;", pos+1))
 +	//		abc9_script = abc9_script.substr(0, pos) + "dretime; retime -o {D};" + abc9_script.substr(pos+8);
  
 -	for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
 -		abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
 +	for (size_t pos = abc9_script.find("{D}"); pos != std::string::npos; pos = abc9_script.find("{D}", pos))
 +		abc9_script = abc9_script.substr(0, pos) + delay_target + abc9_script.substr(pos+3);
  
 -	//for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
 -	//	abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
 +	//for (size_t pos = abc9_script.find("{S}"); pos != std::string::npos; pos = abc9_script.find("{S}", pos))
 +	//	abc9_script = abc9_script.substr(0, pos) + lutin_shared + abc9_script.substr(pos+3);
  
 -	for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos))
 -		abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3);
 +	for (size_t pos = abc9_script.find("{W}"); pos != std::string::npos; pos = abc9_script.find("{W}", pos))
 +		abc9_script = abc9_script.substr(0, pos) + wire_delay + abc9_script.substr(pos+3);
  
+ 	if (nomfs)
 -		for (size_t pos = abc_script.find("&mfs"); pos != std::string::npos; pos = abc_script.find("&mfs", pos))
 -			abc_script = abc_script.erase(pos, strlen("&mfs"));
++		for (size_t pos = abc9_script.find("&mfs"); pos != std::string::npos; pos = abc9_script.find("&mfs", pos))
++			abc9_script = abc9_script.erase(pos, strlen("&mfs"));
+ 
 +	abc9_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
 +	abc9_script = add_echos_to_abc9_cmd(abc9_script);
  
 -	abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str());
 -	abc_script = add_echos_to_abc_cmd(abc_script);
 -
 -	for (size_t i = 0; i+1 < abc_script.size(); i++)
 -		if (abc_script[i] == ';' && abc_script[i+1] == ' ')
 -			abc_script[i+1] = '\n';
 +	for (size_t i = 0; i+1 < abc9_script.size(); i++)
 +		if (abc9_script[i] == ';' && abc9_script[i+1] == ' ')
 +			abc9_script[i+1] = '\n';
  
  	FILE *f = fopen(stringf("%s/abc.script", tempdir_name.c_str()).c_str(), "wt");
 -	fprintf(f, "%s\n", abc_script.c_str());
 +	fprintf(f, "%s\n", abc9_script.c_str());
  	fclose(f);
  
  	if (dff_mode || !clk_str.empty())
diff --cc techlibs/xilinx/synth_xilinx.cc
index 5c2b1402c,1cddd2a92..beefcd451
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -474,14 -474,17 +474,18 @@@ struct SynthXilinxPass : public ScriptP
  				run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
  			else if (abc9) {
  				if (family != "xc7")
 -					log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 -				run("techmap -map +/xilinx/abc_map.v -max_iter 1");
 -				run("read_verilog -icells -lib +/xilinx/abc_model.v");
 -				std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
 +					log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
-                             "will use timing for 'xc7' instead.\n", family.c_str());
++							"will use timing for 'xc7' instead.\n", family.c_str());
 +				run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
 +				run("read_verilog -icells -lib +/xilinx/abc9_model.v");
++				std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
+ 				abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
+ 				abc9_opts += " -nomfs";
  				if (nowidelut)
- 					run("abc9 -lut +/xilinx/abc9_xc7_nowide.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 -					abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
++					abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
  				else
- 					run("abc9 -lut +/xilinx/abc9_xc7.lut -box +/xilinx/abc9_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
 -					abc9_opts += " -lut +/xilinx/abc_xc7.lut";
++					abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
+ 				run("abc9" + abc9_opts);
  			}
  			else {
  				if (nowidelut)