From: Jordi Vaquero <jordi.vaquero@metempsy.com>
Date: Fri, 24 Jul 2020 08:26:15 +0000 (+0200)
Subject: arch-arm: Fix Trap to EL1 on register DC CVAU
X-Git-Tag: v20.1.0.0~395
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5b3a36bf3dbd7197d3ea7eef53347a86ab5fa62;p=gem5.git

arch-arm: Fix Trap to EL1 on register DC CVAU

Change-Id: I8add9fc8595bb1ac0a7de9778bd4544a01b94ee4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31774
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 49cc6b0f8..f9f00f06a 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -146,7 +146,7 @@ MiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg,
         break;
       case MISCREG_DC_CVAU_Xt:
         trap_to_sup = !sctlr.uci && (!hcr.tge || (!scr.ns && !scr.eel2)) &&
-            el == EL1;
+            el == EL0;
         break;
       case MISCREG_CTR_EL0:
         trap_to_sup = el == EL0 && !sctlr.uct &&