From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 06:36:56 +0000 (+0100)
Subject: add get on subvl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5c42ce793e03f6abba4c12193df2cc2893fe64d;p=riscv-isa-sim.git

add get on subvl
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c6d604a..c93c2e5 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -894,6 +894,8 @@ reg_t processor_t::get_csr(int which)
              (state.sv().ssvoffs<<26)     | (state.sv().dsvoffs<<28);
     case CSR_USVMVL:
       return state.sv().mvl;
+    case CSR_USVSUBVL:
+      return state.sv().subvl;
     case CSR_SVREGTOP:
     case CSR_SVREGBOT:
       return 0;// XXX TODO: return correct entry