From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 24 Jun 2020 09:45:38 +0000 (+0200)
Subject: Add or-assignment and plus-assignment tests
X-Git-Tag: working-ls180~445^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5ca4eeefb13c24042bae36ea8f640b5529efd93;p=yosys.git

Add or-assignment and plus-assignment tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys
new file mode 100644
index 000000000..21e08550f
--- /dev/null
+++ b/tests/opt/opt_expr_or_assignment.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a |= i;
+	a |= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys
new file mode 100644
index 000000000..8d8ee5214
--- /dev/null
+++ b/tests/opt/opt_expr_plus_assignment.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a += i;
+	a += j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i