From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 22 Oct 2020 17:19:18 +0000 (+0000)
Subject: add JTAG test
X-Git-Tag: partial-core-ls180-gdsii~39
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5cab8429c047bb450ad0af19df8695afa9e7a4d;p=soclayout.git

add JTAG test
---

diff --git a/experiments10/add.py b/experiments10/add.py
index 68aecc1..9b45f1c 100644
--- a/experiments10/add.py
+++ b/experiments10/add.py
@@ -1,6 +1,16 @@
-from nmigen import *
+# generate add.il ilang file with: python3 add.py
+#
+
+from nmigen import Elaboratable, Signal, Module
 from nmigen.cli import rtlil
 
+# to get c4m-jtag
+# clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
+#            $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
+# for each:  $ python3 setup.py develop --user
+
+from c4m.nmigen.jtag.tap import TAP, IOType
+
 
 class ADD(Elaboratable):
     def __init__(self, width):
@@ -8,9 +18,21 @@ class ADD(Elaboratable):
         self.b   = Signal(width)
         self.f   = Signal(width)
 
+        # set up JTAG
+        self.jtag = TAP(ir_width=4)
+
+        # have to create at least one shift register
+        self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
+
     def elaborate(self, platform):
         m = Module()
+
+        m.submodules.jtag = jtag = self.jtag
+        m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
+
+        # do a simple "add"
         m.d.sync += self.f.eq(self.a + self.b)
+
         return m