From: Michael Snyder Date: Sat, 26 Jul 2003 01:00:33 +0000 (+0000) Subject: 2003-07-25 Michael Snyder X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5de4c570e1b4df0598b2711f611ee28a8d6888b;p=binutils-gdb.git 2003-07-25 Michael Snyder * pshai.s, pshar.s, pshli.s, pshlr.s: New files. * allinsn.exp: Add psha, pshl tests. * pdec.s, pinc.s, padd.s, paddc.s: New files. * allinsn.exp: Add pdec, pinc, padd, paddc tests. * pand.s, pdmsb.s: New files. * allinsn.exp: Add pand, pdmsb tests. --- diff --git a/sim/testsuite/sim/sh/ChangeLog b/sim/testsuite/sim/sh/ChangeLog index 3202a6f0246..832eac48c73 100644 --- a/sim/testsuite/sim/sh/ChangeLog +++ b/sim/testsuite/sim/sh/ChangeLog @@ -1,3 +1,12 @@ +2003-07-25 Michael Snyder + + * pshai.s, pshar.s, pshli.s, pshlr.s: New files. + * allinsn.exp: Add psha, pshl tests. + * pdec.s, pinc.s, padd.s, paddc.s: New files. + * allinsn.exp: Add pdec, pinc, padd, paddc tests. + * pand.s, pdmsb.s: New files. + * allinsn.exp: Add pand, pdmsb tests. + 2003-07-23 Michael Snyder * pmuls.s: New file. diff --git a/sim/testsuite/sim/sh/allinsn.exp b/sim/testsuite/sim/sh/allinsn.exp index 8446bb9cecd..8664af0472e 100644 --- a/sim/testsuite/sim/sh/allinsn.exp +++ b/sim/testsuite/sim/sh/allinsn.exp @@ -24,7 +24,17 @@ if [istarget sh-*elf] { run_sim_test fsqrt.s sh run_sim_test fsub.s sh run_sim_test ftrc.s sh + run_sim_test paddc.s shdsp + run_sim_test padd.s shdsp + run_sim_test pand.s shdsp + run_sim_test pdec.s shdsp + run_sim_test pdmsb.s shdsp + run_sim_test pinc.s shdsp run_sim_test pmuls.s shdsp + run_sim_test pshai.s shdsp + run_sim_test pshar.s shdsp + run_sim_test pshli.s shdsp + run_sim_test pshlr.s shdsp run_sim_test shll.s $all run_sim_test shll2.s $all run_sim_test shll8.s $all diff --git a/sim/testsuite/sim/sh/padd.s b/sim/testsuite/sim/sh/padd.s new file mode 100644 index 00000000000..072935dcdf5 --- /dev/null +++ b/sim/testsuite/sim/sh/padd.s @@ -0,0 +1,54 @@ +# sh testcase for padd +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + padd x0, y0, a0 + assert_sreg 0x4b4b4b4a, a0 + + # 2 + 2 = 4 + mov #2, r0 + lds r0, x0 + lds r0, y0 + padd x0, y0, a0 + assert_sreg 4, a0 + + set_dcfalse + dct padd x0, y0, a1 + assert_sreg2 0xa5a5a5a5, a1 + set_dctrue + dct padd x0, y0, a1 + assert_sreg2 4, a1 + + set_dctrue + dcf padd x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf padd x0, y0, m1 + assert_sreg2 4, m1 + + # padd / pmuls + + padd x0, y0, y0 pmuls x1, y1, m1 + assert_sreg 4, y0 + assert_sreg2 0x3fc838b2, m1 ! (int) 0xa5a5 x (int) 0xa5a5 x 2 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/paddc.s b/sim/testsuite/sim/sh/paddc.s new file mode 100644 index 00000000000..0dd3b67b172 --- /dev/null +++ b/sim/testsuite/sim/sh/paddc.s @@ -0,0 +1,39 @@ +# sh testcase for paddc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + # 2 + 2 = 4 + set_dcfalse + mov #2, r0 + lds r0, x0 + lds r0, y0 + paddc x0, y0, a0 + assert_sreg 4, a0 + + # 2 + 2 + carry = 5 + set_dctrue + paddc x0, y0, a1 + assert_sreg2 5, a1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pand.s b/sim/testsuite/sim/sh/pand.s new file mode 100644 index 00000000000..cddf05892cb --- /dev/null +++ b/sim/testsuite/sim/sh/pand.s @@ -0,0 +1,48 @@ +# sh testcase for pand +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pand x0, y0, a0 + assert_sreg 0xa5a50000, a0 + + # 0xa5a5a5a5 & 0x5a5a5a5a == 0 + set_greg 0x5a5a5a5a r0 + lds r0, x0 + pand x0, y0, a0 + assert_sreg 0, a0 + + set_dcfalse + dct pand x0, y0, m0 + assert_sreg2 0xa5a5a5a5, m0 + set_dctrue + dct pand x0, y0, m0 + assert_sreg2 0, m0 + + set_dctrue + dcf pand x0, y0, m1 + assert_sreg2 0xa5a5a5a5, m1 + set_dcfalse + dcf pand x0, y0, m1 + assert_sreg2 0, m1 + + set_greg 0xa5a5a5a5, r0 + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, a1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pdec.s b/sim/testsuite/sim/sh/pdec.s new file mode 100644 index 00000000000..fa4b6a56e9c --- /dev/null +++ b/sim/testsuite/sim/sh/pdec.s @@ -0,0 +1,110 @@ +# sh testcase for pdec +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pdecx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pdec x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pdec x0, y0 + assert_sreg 0xa5a40000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pdecy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pdec y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pdec y0, x0 + assert_sreg 0xa5a40000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pdmsb.s b/sim/testsuite/sim/sh/pdmsb.s new file mode 100644 index 00000000000..0cb78293265 --- /dev/null +++ b/sim/testsuite/sim/sh/pdmsb.s @@ -0,0 +1,230 @@ +# sh testcase for pdmsb +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x0, x0 +L0: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + set_sreg 0x1, x0 +L1: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0x3, x0 +L2: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0x7, x0 +L3: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xf, x0 +L4: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0x1f, x0 +L5: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0x3f, x0 +L6: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0x7f, x0 +L7: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xff, x0 +L8: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0x1ff, x0 +L9: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0x3ff, x0 +L10: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0x7ff, x0 +L11: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfff, x0 +L12: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0x1fff, x0 +L13: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0x3fff, x0 +L14: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0x7fff, x0 +L15: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff, x0 +L16: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0x1ffff, x0 +L17: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0x3ffff, x0 +L18: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0x7ffff, x0 +L19: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfffff, x0 +L20: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0x1fffff, x0 +L21: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0x3fffff, x0 +L22: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0x7fffff, x0 +L23: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xffffff, x0 +L24: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0x1ffffff, x0 +L25: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0x3ffffff, x0 +L26: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0x7ffffff, x0 +L27: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xfffffff, x0 +L28: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0x1fffffff, x0 +L29: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0x3fffffff, x0 +L30: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x7fffffff, x0 +L31: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0xffffffff, x0 +L32: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + set_sreg 0xfffffffe, x0 +L33: pdmsb x0, x1 + assert_sreg 30<<16, x1 + set_sreg 0xfffffffc, x0 +L34: pdmsb x0, x1 + assert_sreg 29<<16, x1 + set_sreg 0xfffffff8, x0 +L35: pdmsb x0, x1 + assert_sreg 28<<16, x1 + set_sreg 0xfffffff0, x0 +L36: pdmsb x0, x1 + assert_sreg 27<<16, x1 + set_sreg 0xffffffe0, x0 +L37: pdmsb x0, x1 + assert_sreg 26<<16, x1 + set_sreg 0xffffffc0, x0 +L38: pdmsb x0, x1 + assert_sreg 25<<16, x1 + set_sreg 0xffffff80, x0 +L39: pdmsb x0, x1 + assert_sreg 24<<16, x1 + set_sreg 0xffffff00, x0 +L40: pdmsb x0, x1 + assert_sreg 23<<16, x1 + + set_sreg 0xfffffe00, x0 +L41: pdmsb x0, x1 + assert_sreg 22<<16, x1 + set_sreg 0xfffffc00, x0 +L42: pdmsb x0, x1 + assert_sreg 21<<16, x1 + set_sreg 0xfffff800, x0 +L43: pdmsb x0, x1 + assert_sreg 20<<16, x1 + set_sreg 0xfffff000, x0 +L44: pdmsb x0, x1 + assert_sreg 19<<16, x1 + set_sreg 0xffffe000, x0 +L45: pdmsb x0, x1 + assert_sreg 18<<16, x1 + set_sreg 0xffffc000, x0 +L46: pdmsb x0, x1 + assert_sreg 17<<16, x1 + set_sreg 0xffff8000, x0 +L47: pdmsb x0, x1 + assert_sreg 16<<16, x1 + set_sreg 0xffff0000, x0 +L48: pdmsb x0, x1 + assert_sreg 15<<16, x1 + + set_sreg 0xfffe0000, x0 +L49: pdmsb x0, x1 + assert_sreg 14<<16, x1 + set_sreg 0xfffc0000, x0 +L50: pdmsb x0, x1 + assert_sreg 13<<16, x1 + set_sreg 0xfff80000, x0 +L51: pdmsb x0, x1 + assert_sreg 12<<16, x1 + set_sreg 0xfff00000, x0 +L52: pdmsb x0, x1 + assert_sreg 11<<16, x1 + set_sreg 0xffe00000, x0 +L53: pdmsb x0, x1 + assert_sreg 10<<16, x1 + set_sreg 0xffc00000, x0 +L54: pdmsb x0, x1 + assert_sreg 9<<16, x1 + set_sreg 0xff800000, x0 +L55: pdmsb x0, x1 + assert_sreg 8<<16, x1 + set_sreg 0xff000000, x0 +L56: pdmsb x0, x1 + assert_sreg 7<<16, x1 + + set_sreg 0xfe000000, x0 +L57: pdmsb x0, x1 + assert_sreg 6<<16, x1 + set_sreg 0xfc000000, x0 +L58: pdmsb x0, x1 + assert_sreg 5<<16, x1 + set_sreg 0xf8000000, x0 +L59: pdmsb x0, x1 + assert_sreg 4<<16, x1 + set_sreg 0xf0000000, x0 +L60: pdmsb x0, x1 + assert_sreg 3<<16, x1 + set_sreg 0xe0000000, x0 +L61: pdmsb x0, x1 + assert_sreg 2<<16, x1 + set_sreg 0xc0000000, x0 +L62: pdmsb x0, x1 + assert_sreg 1<<16, x1 + set_sreg 0x80000000, x0 +L63: pdmsb x0, x1 + assert_sreg 0<<16, x1 + set_sreg 0x00000000, x0 +L64: pdmsb x0, x1 +# assert_sreg 31<<16, x1 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pinc.s b/sim/testsuite/sim/sh/pinc.s new file mode 100644 index 00000000000..0067bc00ebe --- /dev/null +++ b/sim/testsuite/sim/sh/pinc.s @@ -0,0 +1,110 @@ +# sh testcase for pinc +# mach: shdsp +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dct_pincx: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dcfalse + dct pinc x0, y0 + assert_sreg 0xa5a5a5a5, y0 + set_dctrue + dct pinc x0, y0 + assert_sreg 0xa5a60000, y0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + +dcf_pincy: + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_dctrue + dcf pinc y0, x0 + assert_sreg 0xa5a5a5a5, x0 + set_dcfalse + dcf pinc y0, x0 + assert_sreg 0xa5a60000, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + pass + exit 0 diff --git a/sim/testsuite/sim/sh/pshai.s b/sim/testsuite/sim/sh/pshai.s new file mode 100644 index 00000000000..b2cdbbc81b8 --- /dev/null +++ b/sim/testsuite/sim/sh/pshai.s @@ -0,0 +1,200 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_imm: ! shift arithmetic, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, a0 + psha #0, a0 + assert_sreg 0x1, a0 + psha #-0, a0 + assert_sreg 0x1, a0 + + psha #1, a0 + assert_sreg 0x2, a0 + psha #-1, a0 + assert_sreg 0x1, a0 + + psha #2, a0 + assert_sreg 0x4, a0 + psha #-2, a0 + assert_sreg 0x1, a0 + + psha #3, a0 + assert_sreg 0x8, a0 + psha #-3, a0 + assert_sreg 0x1, a0 + + psha #4, a0 + assert_sreg 0x10, a0 + psha #-4, a0 + assert_sreg 0x1, a0 + + psha #5, a0 + assert_sreg 0x20, a0 + psha #-5, a0 + assert_sreg 0x1, a0 + + psha #6, a0 + assert_sreg 0x40, a0 + psha #-6, a0 + assert_sreg 0x1, a0 + + psha #7, a0 + assert_sreg 0x80, a0 + psha #-7, a0 + assert_sreg 0x1, a0 + + psha #8, a0 + assert_sreg 0x100, a0 + psha #-8, a0 + assert_sreg 0x1, a0 + + psha #9, a0 + assert_sreg 0x200, a0 + psha #-9, a0 + assert_sreg 0x1, a0 + + psha #10, a0 + assert_sreg 0x400, a0 + psha #-10, a0 + assert_sreg 0x1, a0 + + psha #11, a0 + assert_sreg 0x800, a0 + psha #-11, a0 + assert_sreg 0x1, a0 + + psha #12, a0 + assert_sreg 0x1000, a0 + psha #-12, a0 + assert_sreg 0x1, a0 + + psha #13, a0 + assert_sreg 0x2000, a0 + psha #-13, a0 + assert_sreg 0x1, a0 + + psha #14, a0 + assert_sreg 0x4000, a0 + psha #-14, a0 + assert_sreg 0x1, a0 + + psha #15, a0 + assert_sreg 0x8000, a0 + psha #-15, a0 + assert_sreg 0x1, a0 + + psha #16, a0 + assert_sreg 0x10000, a0 + psha #-16, a0 + assert_sreg 0x1, a0 + + psha #17, a0 + assert_sreg 0x20000, a0 + psha #-17, a0 + assert_sreg 0x1, a0 + + psha #18, a0 + assert_sreg 0x40000, a0 + psha #-18, a0 + assert_sreg 0x1, a0 + + psha #19, a0 + assert_sreg 0x80000, a0 + psha #-19, a0 + assert_sreg 0x1, a0 + + psha #20, a0 + assert_sreg 0x100000, a0 + psha #-20, a0 + assert_sreg 0x1, a0 + + psha #21, a0 + assert_sreg 0x200000, a0 + psha #-21, a0 + assert_sreg 0x1, a0 + + psha #22, a0 + assert_sreg 0x400000, a0 + psha #-22, a0 + assert_sreg 0x1, a0 + + psha #23, a0 + assert_sreg 0x800000, a0 + psha #-23, a0 + assert_sreg 0x1, a0 + + psha #24, a0 + assert_sreg 0x1000000, a0 + psha #-24, a0 + assert_sreg 0x1, a0 + + psha #25, a0 + assert_sreg 0x2000000, a0 + psha #-25, a0 + assert_sreg 0x1, a0 + + psha #26, a0 + assert_sreg 0x4000000, a0 + psha #-26, a0 + assert_sreg 0x1, a0 + + psha #27, a0 + assert_sreg 0x8000000, a0 + psha #-27, a0 + assert_sreg 0x1, a0 + + psha #28, a0 + assert_sreg 0x10000000, a0 + psha #-28, a0 + assert_sreg 0x1, a0 + + psha #29, a0 + assert_sreg 0x20000000, a0 + psha #-29, a0 + assert_sreg 0x1, a0 + + psha #30, a0 + assert_sreg 0x40000000, a0 + psha #-30, a0 + assert_sreg 0x1, a0 + + psha #31, a0 + assert_sreg 0x80000000, a0 + psha #-31, a0 + assert_sreg 0xffffffff, a0 + + psha #32, a0 + assert_sreg 0x00000000, a0 +# I don't grok what should happen here... +# psha #-32, a0 +# assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshar.s b/sim/testsuite/sim/sh/pshar.s new file mode 100644 index 00000000000..01c4b5fdef2 --- /dev/null +++ b/sim/testsuite/sim/sh/pshar.s @@ -0,0 +1,265 @@ +# sh testcase for psha +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +psha_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x1, x0 + set_sreg 0x0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x10000, y0 + psha x0, y0, x0 + assert_sreg 0x2, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x20000, y0 + psha x0, y0, x0 + assert_sreg 0x4, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x30000, y0 + psha x0, y0, x0 + assert_sreg 0x8, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x40000, y0 + psha x0, y0, x0 + assert_sreg 0x10, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x50000, y0 + psha x0, y0, x0 + assert_sreg 0x20, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x60000, y0 + psha x0, y0, x0 + assert_sreg 0x40, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x70000, y0 + psha x0, y0, x0 + assert_sreg 0x80, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x80000, y0 + psha x0, y0, x0 + assert_sreg 0x100, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x90000, y0 + psha x0, y0, x0 + assert_sreg 0x200, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xa0000, y0 + psha x0, y0, x0 + assert_sreg 0x400, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xb0000, y0 + psha x0, y0, x0 + assert_sreg 0x800, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xc0000, y0 + psha x0, y0, x0 + assert_sreg 0x1000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xd0000, y0 + psha x0, y0, x0 + assert_sreg 0x2000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xe0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0xf0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x100000, y0 + psha x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x110000, y0 + psha x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x120000, y0 + psha x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x130000, y0 + psha x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x140000, y0 + psha x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x150000, y0 + psha x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x160000, y0 + psha x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x170000, y0 + psha x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x180000, y0 + psha x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x190000, y0 + psha x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1a0000, y0 + psha x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1b0000, y0 + psha x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1c0000, y0 + psha x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1d0000, y0 + psha x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1e0000, y0 + psha x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0x1, x0 + + set_sreg 0x1f0000, y0 + psha x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + psha x0, y0, x0 + assert_sreg 0xffffffff, x0 + + set_sreg 0x200000, y0 + psha x0, y0, x0 + assert_sreg 0x00000000, x0 +# I don't grok what should happen here... +# pneg y0, y0 +# psha x0, y0, x0 +# assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshli.s b/sim/testsuite/sim/sh/pshli.s new file mode 100644 index 00000000000..a6616e896ac --- /dev/null +++ b/sim/testsuite/sim/sh/pshli.s @@ -0,0 +1,119 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_imm: ! shift logical, immediate operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, a0 + pshl #0, a0 + assert_sreg 0x10000, a0 + pshl #-0, a0 + assert_sreg 0x10000, a0 + + pshl #1, a0 + assert_sreg 0x20000, a0 + pshl #-1, a0 + assert_sreg 0x10000, a0 + + pshl #2, a0 + assert_sreg 0x40000, a0 + pshl #-2, a0 + assert_sreg 0x10000, a0 + + pshl #3, a0 + assert_sreg 0x80000, a0 + pshl #-3, a0 + assert_sreg 0x10000, a0 + + pshl #4, a0 + assert_sreg 0x100000, a0 + pshl #-4, a0 + assert_sreg 0x10000, a0 + + pshl #5, a0 + assert_sreg 0x200000, a0 + pshl #-5, a0 + assert_sreg 0x10000, a0 + + pshl #6, a0 + assert_sreg 0x400000, a0 + pshl #-6, a0 + assert_sreg 0x10000, a0 + + pshl #7, a0 + assert_sreg 0x800000, a0 + pshl #-7, a0 + assert_sreg 0x10000, a0 + + pshl #8, a0 + assert_sreg 0x1000000, a0 + pshl #-8, a0 + assert_sreg 0x10000, a0 + + pshl #9, a0 + assert_sreg 0x2000000, a0 + pshl #-9, a0 + assert_sreg 0x10000, a0 + + pshl #10, a0 + assert_sreg 0x4000000, a0 + pshl #-10, a0 + assert_sreg 0x10000, a0 + + pshl #11, a0 + assert_sreg 0x8000000, a0 + pshl #-11, a0 + assert_sreg 0x10000, a0 + + pshl #12, a0 + assert_sreg 0x10000000, a0 + pshl #-12, a0 + assert_sreg 0x10000, a0 + + pshl #13, a0 + assert_sreg 0x20000000, a0 + pshl #-13, a0 + assert_sreg 0x10000, a0 + + pshl #14, a0 + assert_sreg 0x40000000, a0 + pshl #-14, a0 + assert_sreg 0x10000, a0 + + pshl #15, a0 + assert_sreg 0x80000000, a0 + pshl #-15, a0 + assert_sreg 0x10000, a0 + + pshl #16, a0 + assert_sreg 0x00000000, a0 + pshl #-16, a0 + assert_sreg 0x0, a0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x0 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y0 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 + diff --git a/sim/testsuite/sim/sh/pshlr.s b/sim/testsuite/sim/sh/pshlr.s new file mode 100644 index 00000000000..36cb47f4188 --- /dev/null +++ b/sim/testsuite/sim/sh/pshlr.s @@ -0,0 +1,152 @@ +# sh testcase for pshl +# mach: all +# as(sh): -defsym sim_cpu=0 +# as(shdsp): -defsym sim_cpu=1 -dsp + + .include "testutils.inc" + + start + +pshl_reg: ! shift arithmetic, register operand + set_grs_a5a5 + lds r0, a0 + pcopy a0, a1 + lds r0, x0 + lds r0, x1 + lds r0, y0 + lds r0, y1 + pcopy x0, m0 + pcopy y1, m1 + + set_sreg 0x10000, x0 + set_sreg 0x0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x10000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x20000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x30000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x40000, y0 + pshl x0, y0, x0 + assert_sreg 0x100000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x50000, y0 + pshl x0, y0, x0 + assert_sreg 0x200000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x60000, y0 + pshl x0, y0, x0 + assert_sreg 0x400000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x70000, y0 + pshl x0, y0, x0 + assert_sreg 0x800000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x80000, y0 + pshl x0, y0, x0 + assert_sreg 0x1000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x90000, y0 + pshl x0, y0, x0 + assert_sreg 0x2000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xa0000, y0 + pshl x0, y0, x0 + assert_sreg 0x4000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xb0000, y0 + pshl x0, y0, x0 + assert_sreg 0x8000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xc0000, y0 + pshl x0, y0, x0 + assert_sreg 0x10000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xd0000, y0 + pshl x0, y0, x0 + assert_sreg 0x20000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xe0000, y0 + pshl x0, y0, x0 + assert_sreg 0x40000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0xf0000, y0 + pshl x0, y0, x0 + assert_sreg 0x80000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x10000, x0 + + set_sreg 0x100000, y0 + pshl x0, y0, x0 + assert_sreg 0x00000000, x0 + pneg y0, y0 + pshl x0, y0, x0 + assert_sreg 0x0, x0 + + test_grs_a5a5 + assert_sreg2 0xa5a5a5a5, a0 + assert_sreg2 0xa5a5a5a5, a1 + assert_sreg 0xa5a5a5a5, x1 + assert_sreg 0xa5a5a5a5, y1 + assert_sreg2 0xa5a5a5a5, m0 + assert_sreg2 0xa5a5a5a5, m1 + + + pass + exit 0 +