From: lkcl Date: Wed, 19 Apr 2023 15:10:23 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5e78b3b42d2eff1ba11b30c17bcb66d311aa3d6;p=libreriscv.git --- diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn index 8b9b7f824..1d314b6cb 100644 --- a/openpower/sv/normal.mdwn +++ b/openpower/sv/normal.mdwn @@ -17,8 +17,7 @@ Table of contents: Mode is an augmentation of SV behaviour, providing additional functionality. Some of these alterations are element-based (saturation), -others involve post-analysis (predicate result) and others are -Vector-based (mapreduce, fail-on-first). +others are Vector-based (mapreduce, fail-on-first). [[sv/ldst]], [[sv/cr_ops]] and [[sv/branches]] are covered separately: the following Modes apply to Arithmetic and Logical SVP64 operations: