From: Daniel Kucera <daniel.kucera@gmail.com>
Date: Tue, 13 Aug 2019 08:14:16 +0000 (+0200)
Subject: more understandable error when missing a memory
X-Git-Tag: 24jan2021_ls180~1052^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5eaf172c5411902555b1f62ec1ffeaa57377ac3;p=litex.git

more understandable error when missing a memory
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index c70a9c90..f2a09627 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -501,7 +501,7 @@ class SoCCore(Module):
         if self.cpu_type is not None:
             for mem in "rom", "sram":
                 if mem not in registered_mems:
-                    raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem))
+                    raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem))
 
         # Add the Wishbone Masters/Slaves interconnect
         if len(self._wb_masters):