From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 5 Apr 2019 23:20:43 +0000 (-0700)
Subject: Move dffinit til after abc
X-Git-Tag: yosys-0.9~171^2~18
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5f33b5409d9325730204eb776e0046726d55d2c;p=yosys.git

Move dffinit til after abc
---

diff --git a/techlibs/xilinx/.synth_xilinx.cc.swn b/techlibs/xilinx/.synth_xilinx.cc.swn
deleted file mode 100644
index a6564691a..000000000
Binary files a/techlibs/xilinx/.synth_xilinx.cc.swn and /dev/null differ
diff --git a/techlibs/xilinx/.synth_xilinx.cc.swo b/techlibs/xilinx/.synth_xilinx.cc.swo
deleted file mode 100644
index 6fc27ed3b..000000000
Binary files a/techlibs/xilinx/.synth_xilinx.cc.swo and /dev/null differ
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index ee8dec9ee..2676f5915 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -284,8 +284,6 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
 			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/cells_map.v");
-			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
-					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			Pass::call(design, "clean");
 		}
 
@@ -295,6 +293,8 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v");
+			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 		}
 
 		if (check_label(active, run_from, run_to, "check"))