From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Jun 2020 15:03:46 +0000 (+0100)
Subject: first unit test for div
X-Git-Tag: div_pipeline~199
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a5fff4bc760cc84a503db80177c38ff0b8660b79;p=soc.git

first unit test for div
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 5571571b..e26e04fa 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -77,38 +77,8 @@ class DIVTestCase(FHDLTestCase):
         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs)
         self.test_data.append(tc)
 
-    def test_1_regression(self):
-        lst = [f"extsw 3, 1"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0xb6a1fc6c8576af91
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"subf 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x3d7f3f7ca24bac7b
-        initial_regs[2] = 0xf6b2ac5e13ee15c2
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"subf 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x833652d96c7c0058
-        initial_regs[2] = 0x1c27ecff8a086c1a
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"extsb 3, 1"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x7f9497aaff900ea0
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"add. 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0xc523e996a8ff6215
-        initial_regs[2] = 0xe1e5b9cc9864c4a8
-        self.run_tst_program(Program(lst), initial_regs)
-        lst = [f"add 3, 1, 2"]
-        initial_regs = [0] * 32
-        initial_regs[1] = 0x2e08ae202742baf8
-        initial_regs[2] = 0x86c43ece9efe5baa
-        self.run_tst_program(Program(lst), initial_regs)
-
-    def test_rand(self):
-        insns = ["add", "add.", "subf"]
+    def test_rand_divw(self):
+        insns = ["divw", "divw.", "divwo", "divwo."]
         for i in range(40):
             choice = random.choice(insns)
             lst = [f"{choice} 3, 1, 2"]
@@ -117,55 +87,6 @@ class DIVTestCase(FHDLTestCase):
             initial_regs[2] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
-    def test_rand_imm(self):
-        insns = ["addi", "addis", "subfic"]
-        for i in range(10):
-            choice = random.choice(insns)
-            imm = random.randint(-(1<<15), (1<<15)-1)
-            lst = [f"{choice} 3, 1, {imm}"]
-            print(lst)
-            initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
-
-    def test_0_adde(self):
-        lst = ["adde. 5, 6, 7"]
-        for i in range(10):
-            initial_regs = [0] * 32
-            initial_regs[6] = random.randint(0, (1<<64)-1)
-            initial_regs[7] = random.randint(0, (1<<64)-1)
-            initial_sprs = {}
-            xer = SelectableInt(0, 64)
-            xer[XER_bits['CA']] = 1
-            initial_sprs[special_sprs['XER']] = xer
-            self.run_tst_program(Program(lst), initial_regs, initial_sprs)
-
-    def test_cmp(self):
-        lst = ["subf. 1, 6, 7",
-               "cmp cr2, 1, 6, 7"]
-        initial_regs = [0] * 32
-        initial_regs[6] = 0x10
-        initial_regs[7] = 0x05
-        self.run_tst_program(Program(lst), initial_regs, {})
-
-    def test_extsb(self):
-        insns = ["extsb", "extsh", "extsw"]
-        for i in range(10):
-            choice = random.choice(insns)
-            lst = [f"{choice} 3, 1"]
-            print(lst)
-            initial_regs = [0] * 32
-            initial_regs[1] = random.randint(0, (1<<64)-1)
-            self.run_tst_program(Program(lst), initial_regs)
-
-    def test_cmpeqb(self):
-        lst = ["cmpeqb cr1, 1, 2"]
-        for i in range(20):
-            initial_regs = [0] * 32
-            initial_regs[1] = i
-            initial_regs[2] = 0x0001030507090b0f
-            self.run_tst_program(Program(lst), initial_regs, {})
-
     def test_ilang(self):
         pspec = DIVPipeSpec(id_wid=2)
         alu = DIVBasePipe(pspec)