From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sat, 9 May 2015 23:39:39 +0000 (-0700)
Subject: Update to privileged architecture version 1.7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a60626553be99d69f879464dbeb71ffe1ff80c75;p=riscv-tests.git

Update to privileged architecture version 1.7
---

diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S
index 97b90d5..dc16228 100644
--- a/benchmarks/common/crt.S
+++ b/benchmarks/common/crt.S
@@ -67,23 +67,13 @@ _start:
   li t0, MSTATUS_FS;   csrs mstatus, t0    # enable FPU
   li t0, MSTATUS_XS;   csrs mstatus, t0    # enable accelerator
 
-  li t0, ((MSTATUS64_UA & ~(MSTATUS64_UA << 1)) * UA_RV64) >> 31
-  sll t0, t0, 31
-  li t1, ((MSTATUS64_SA & ~(MSTATUS64_SA << 1)) * UA_RV64) >> 31
-  sll t1, t1, 31
 #ifdef __riscv64
+  csrr t0, mcpuid
   # make sure processor supports RV64 if this was compiled for RV64
-  bnez t0, 1f
+  bltz t0, 1f
   li a0, 1234
   j tohost_exit
 1:
-  # enable RV64 for user and supervisor
-  csrs mstatus, t0
-  csrs mstatus, t1
-#else
-  # disable RV64 for user and supervisor
-  csrc mstatus, t0
-  csrc mstatus, t1
 #endif
 
   csrr t0, mstatus
@@ -138,7 +128,7 @@ _start:
   and tp, tp, -64
 
   # get core id
-  csrr a0, hartid
+  csrr a0, mhartid
   # for now, assume only 1 core
   li a1, 1
 1:bgeu a0, a1, 1b
diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c
index 3c08bc2..0975acd 100644
--- a/benchmarks/common/syscalls.c
+++ b/benchmarks/common/syscalls.c
@@ -22,8 +22,8 @@ static long handle_frontend_syscall(long which, long arg0, long arg1, long arg2)
   magic_mem[2] = arg1;
   magic_mem[3] = arg2;
   __sync_synchronize();
-  write_csr(tohost, (long)magic_mem);
-  while (swap_csr(fromhost, 0) == 0);
+  write_csr(mtohost, (long)magic_mem);
+  while (swap_csr(mfromhost, 0) == 0);
   return magic_mem[0];
 }
 
@@ -62,7 +62,7 @@ static int handle_stats(int enable)
 
 void tohost_exit(long code)
 {
-  write_csr(tohost, (code << 1) | 1);
+  write_csr(mtohost, (code << 1) | 1);
   while (1);
 }
 
@@ -75,7 +75,7 @@ long handle_trap(long cause, long epc, long long regs[32])
   if (cause == CAUSE_ILLEGAL_INSTRUCTION &&
       (*(int*)epc & *csr_insn) == *csr_insn)
     ;
-  else if (cause != CAUSE_ECALL)
+  else if (cause != CAUSE_USER_ECALL)
     tohost_exit(1337);
   else if (regs[17] == SYS_exit)
     tohost_exit(regs[10]);
diff --git a/benchmarks/common/test.ld b/benchmarks/common/test.ld
index 082891c..db4ec45 100644
--- a/benchmarks/common/test.ld
+++ b/benchmarks/common/test.ld
@@ -21,7 +21,7 @@ SECTIONS
 {
 
   /* text: test code section */
-  . = 0;
+  . = 0x100;
   .text : 
   {
     crt.o(.text)
diff --git a/env b/env
index 57b1adb..04b236a 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 57b1adbf48ad588366c8f88d91e4c165feb3dae1
+Subproject commit 04b236aac5369e4c744796cabf6304324a48fe7d
diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
index db40dc1..52f6462 100644
--- a/isa/rv64mi/Makefrag
+++ b/isa/rv64mi/Makefrag
@@ -5,6 +5,7 @@
 rv64mi_sc_tests = \
 	dirty \
 	csr \
+	mcsr \
 	illegal \
 	ma_fetch \
 	ma_addr \
diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
index 1cf429a..2be4921 100644
--- a/isa/rv64mi/dirty.S
+++ b/isa/rv64mi/dirty.S
@@ -74,9 +74,9 @@ die:
 
 .data
 .align 12
-page_table_1: .dword PTE_TYPE_US_SRX
+page_table_1: .dword PTE_V | PTE_TYPE_URX_SRX
 dummy: .dword 0
 .align 12
-page_table_2: .dword PTE_TYPE_US_SRWX
+page_table_2: .dword PTE_V | PTE_TYPE_URWX_SRWX
 
 RVTEST_CODE_END
diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
index 326476d..457a9cd 100644
--- a/isa/rv64mi/ipi.S
+++ b/isa/rv64mi/ipi.S
@@ -15,6 +15,7 @@ RVTEST_CODE_BEGIN
 
   # enable interrupts
   csrs mstatus, MSTATUS_IE
+  csrs mie, MIP_MSIP
 
   # get a unique core id
   la a0, coreid
@@ -30,7 +31,7 @@ RVTEST_CODE_BEGIN
   bltu a1, a3, 1b
 
   # IPI dominoes
-  csrr a0, hartid
+  csrr a0, mhartid
   1: bnez a0, 1b
   add a0, a0, 1
   rem a0, a0, a3
@@ -38,7 +39,7 @@ RVTEST_CODE_BEGIN
   1: j 1b
 
 mtvec_handler:
-  csrr a0, hartid
+  csrr a0, mhartid
   bnez a0, 2f
   RVTEST_PASS
 
diff --git a/isa/rv64mi/mcsr.S b/isa/rv64mi/mcsr.S
new file mode 100644
index 0000000..c1e2cd3
--- /dev/null
+++ b/isa/rv64mi/mcsr.S
@@ -0,0 +1,30 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# mcsr.S
+#-----------------------------------------------------------------------------
+#
+# Test various M-mode CSRs.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Check that mcpuid reports RV64
+  TEST_CASE(2, a0, 0x2, csrr a0, mcpuid; srl a0, a0, 62)
+
+  # Check that mhartid reports 0
+  TEST_CASE(3, a0, 0x0, csrr a0, mhartid)
+
+  # Check that mimpid reports UC Berkeley
+  TEST_CASE(4, a0, 0x1, csrr a0, mimpid; sll a0, a0, 48; srl a0, a0, 48)
+
+  # Check that mtvec reports DEFAULT_MTVEC
+  TEST_CASE(5, a0, DEFAULT_MTVEC, csrr a0, mtvec)
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 5d4b309..d66b432 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN
   #define SSTATUS_PS MSTATUS_PRV1
 #endif
 
-  csrwi scycle, 0
+  csrwi cyclew, 0
 
   csrwi sscratch, 3
   TEST_CASE( 2, a0,         3, csrr a0, sscratch);
@@ -85,7 +85,7 @@ privileged:
 syscall:
   # Make sure scause indicates a syscall.
   csrr t0, scause
-  li t1, CAUSE_ECALL
+  li t1, CAUSE_USER_ECALL
   bne t0, t1, fail
 
   # We're done.
diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index e1c13b6..935b2dd 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -19,6 +19,8 @@ RVTEST_CODE_BEGIN
   #define scause mcause
   #define sepc mepc
   #define stvec_handler mtvec_handler
+  #undef CAUSE_SUPERVISOR_ECALL
+  #define CAUSE_SUPERVISOR_ECALL CAUSE_MACHINE_ECALL
 #endif
 
   li TESTNUM, 2
@@ -30,7 +32,7 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
 stvec_handler:
-  li t1, CAUSE_ECALL
+  li t1, CAUSE_SUPERVISOR_ECALL
   csrr t0, scause
   bne t0, t1, fail
   csrr t0, sepc
diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S
index c78d922..9909d41 100644
--- a/isa/rv64si/timer.S
+++ b/isa/rv64si/timer.S
@@ -16,23 +16,28 @@ RVTEST_CODE_BEGIN
 #ifdef __MACHINE_MODE
   #define sscratch mscratch
   #define sstatus mstatus
+  #define sie mie
   #define scause mcause
   #define sepc mepc
   #define stvec_handler mtvec_handler
   #undef SSTATUS_PS
   #define SSTATUS_PS MSTATUS_PRV1
-  #undef SSTATUS_IE
-  #define SSTATUS_IE MSTATUS_IE
-  #undef SSTATUS_TIE
-  #define SSTATUS_TIE MSTATUS_STIE
+  #undef SIP_STIP
+  #define SIP_STIP MIP_STIP
 #endif
 
+#define DELTA_T 999
+
   li s8, 0         # number of taken timer interrupts
   li s9, 10        # how many interrupts to run for
-  csrw stimecmp, 1
-  csrw stime, 0
-  li a0, SSTATUS_IE | SSTATUS_TIE
-  csrs sstatus, a0
+
+  .align 4
+  csrr a0, stime
+  add a0, a0, DELTA_T
+  csrw stimecmp, a0
+  li a0, SIP_STIP
+  csrs sie, a0
+  csrs sstatus, SSTATUS_IE
 
   # jump to user land
   li t0, SSTATUS_PS
@@ -79,7 +84,7 @@ stvec_handler:
   bnez t0, fail
 
   csrr t0, stime
-  addi t0, t0, 999
+  addi t0, t0, DELTA_T
   csrw stimecmp, t0
 
   add s8, s8, 1