From: Gabe Black Date: Wed, 9 Sep 2020 00:46:39 +0000 (-0700) Subject: cpu: Fix style and add overrides to bas_dyn_inst.hh. X-Git-Tag: v20.1.0.0~56 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a607c250d961b45363b3f3a7c25f37a00c863d17;p=gem5.git cpu: Fix style and add overrides to bas_dyn_inst.hh. Either return types, brackets and the function body should all be on their own line, or the entire function should be on a single line. Consistently place the * or & up against the variable name and not the type name. There isn't an official rule for which to use, but the majority of existing uses were this way. Add overrides for overridden virtual methods. These fixes get rid of compiler warnings which are breaking the build for me. Change-Id: Ifc6ace4794a66ffd031ee686f6b6ef888004d786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34216 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index b0e9ef267..56b9114d2 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -291,30 +291,34 @@ class BaseDynInst : public ExecContext, public RefCounted // //////////////////////////////////////////// - void demapPage(Addr vaddr, uint64_t asn) + void + demapPage(Addr vaddr, uint64_t asn) override { cpu->demapPage(vaddr, asn); } - void demapInstPage(Addr vaddr, uint64_t asn) + void + demapInstPage(Addr vaddr, uint64_t asn) { cpu->demapPage(vaddr, asn); } - void demapDataPage(Addr vaddr, uint64_t asn) + void + demapDataPage(Addr vaddr, uint64_t asn) { cpu->demapPage(vaddr, asn); } Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byte_enable = std::vector()); + const std::vector &byte_enable=std::vector()) override; Fault initiateHtmCmd(Request::Flags flags) override; Fault writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byte_enable = std::vector()); + const std::vector &byte_enable=std::vector()) + override; Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags, - AtomicOpFunctorPtr amo_op); + AtomicOpFunctorPtr amo_op) override; /** True if the DTB address translation has started. */ bool translationStarted() const { return instFlags[TranslationStarted]; } @@ -329,8 +333,16 @@ class BaseDynInst : public ExecContext, public RefCounted * snoop invalidate modifies the line, in which case we need to squash. * If nothing modified the line the order doesn't matter. */ - bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; } - void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; } + bool + possibleLoadViolation() const + { + return instFlags[PossibleLoadViolation]; + } + void + possibleLoadViolation(bool f) + { + instFlags[PossibleLoadViolation] = f; + } /** True if the address hit a external snoop while sitting in the LSQ. * If this is true and a older instruction sees it, this instruction must @@ -343,7 +355,8 @@ class BaseDynInst : public ExecContext, public RefCounted * Returns true if the DTB address translation is being delayed due to a hw * page table walk. */ - bool isTranslationDelayed() const + bool + isTranslationDelayed() const { return (translationStarted() && !translationCompleted()); } @@ -356,13 +369,15 @@ class BaseDynInst : public ExecContext, public RefCounted /** Returns the physical register index of the i'th destination * register. */ - PhysRegIdPtr renamedDestRegIdx(int idx) const + PhysRegIdPtr + renamedDestRegIdx(int idx) const { return _destRegIdx[idx]; } /** Returns the physical register index of the i'th source register. */ - PhysRegIdPtr renamedSrcRegIdx(int idx) const + PhysRegIdPtr + renamedSrcRegIdx(int idx) const { assert(TheISA::MaxInstSrcRegs > idx); return _srcRegIdx[idx]; @@ -371,7 +386,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Returns the flattened register index of the i'th destination * register. */ - const RegId& flattenedDestRegIdx(int idx) const + const RegId & + flattenedDestRegIdx(int idx) const { return _flatDestRegIdx[idx]; } @@ -379,7 +395,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Returns the physical register index of the previous physical register * that remapped to the same logical register index. */ - PhysRegIdPtr prevDestRegIdx(int idx) const + PhysRegIdPtr + prevDestRegIdx(int idx) const { return _prevDestRegIdx[idx]; } @@ -387,9 +404,9 @@ class BaseDynInst : public ExecContext, public RefCounted /** Renames a destination register to a physical register. Also records * the previous physical register that the logical register mapped to. */ - void renameDestReg(int idx, - PhysRegIdPtr renamed_dest, - PhysRegIdPtr previous_rename) + void + renameDestReg(int idx, PhysRegIdPtr renamed_dest, + PhysRegIdPtr previous_rename) { _destRegIdx[idx] = renamed_dest; _prevDestRegIdx[idx] = previous_rename; @@ -401,7 +418,8 @@ class BaseDynInst : public ExecContext, public RefCounted * has/will produce that logical register's result. * @todo: add in whether or not the source register is ready. */ - void renameSrcReg(int idx, PhysRegIdPtr renamed_src) + void + renameSrcReg(int idx, PhysRegIdPtr renamed_src) { _srcRegIdx[idx] = renamed_src; } @@ -409,7 +427,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Flattens a destination architectural register index into a logical * index. */ - void flattenDestReg(int idx, const RegId& flattened_dest) + void + flattenDestReg(int idx, const RegId &flattened_dest) { _flatDestRegIdx[idx] = flattened_dest; } @@ -469,10 +488,7 @@ class BaseDynInst : public ExecContext, public RefCounted bool doneTargCalc() { return false; } /** Set the predicted target of this current instruction. */ - void setPredTarg(const TheISA::PCState &_predPC) - { - predPC = _predPC; - } + void setPredTarg(const TheISA::PCState &_predPC) { predPC = _predPC; } const TheISA::PCState &readPredTarg() { return predPC; } @@ -486,18 +502,17 @@ class BaseDynInst : public ExecContext, public RefCounted Addr predMicroPC() { return predPC.microPC(); } /** Returns whether the instruction was predicted taken or not. */ - bool readPredTaken() - { - return instFlags[PredTaken]; - } + bool readPredTaken() { return instFlags[PredTaken]; } - void setPredTaken(bool predicted_taken) + void + setPredTaken(bool predicted_taken) { instFlags[PredTaken] = predicted_taken; } /** Returns whether the instruction mispredicted. */ - bool mispredicted() + bool + mispredicted() { TheISA::PCState tempPC = pc; TheISA::advancePC(tempPC, staticInst); @@ -529,10 +544,16 @@ class BaseDynInst : public ExecContext, public RefCounted bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); } bool isThreadSync() const { return staticInst->isThreadSync(); } bool isSerializing() const { return staticInst->isSerializing(); } - bool isSerializeBefore() const - { return staticInst->isSerializeBefore() || status[SerializeBefore]; } - bool isSerializeAfter() const - { return staticInst->isSerializeAfter() || status[SerializeAfter]; } + bool + isSerializeBefore() const + { + return staticInst->isSerializeBefore() || status[SerializeBefore]; + } + bool + isSerializeAfter() const + { + return staticInst->isSerializeAfter() || status[SerializeAfter]; + } bool isSquashAfter() const { return staticInst->isSquashAfter(); } bool isMemBarrier() const { return staticInst->isMemBarrier(); } bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } @@ -553,24 +574,28 @@ class BaseDynInst : public ExecContext, public RefCounted bool isHtmCancel() const { return staticInst->isHtmCancel(); } bool isHtmCmd() const { return staticInst->isHtmCmd(); } - uint64_t getHtmTransactionUid() const override + uint64_t + getHtmTransactionUid() const override { assert(instFlags[HtmFromTransaction]); return this->htmUid; } - uint64_t newHtmTransactionUid() const override + uint64_t + newHtmTransactionUid() const override { panic("Not yet implemented\n"); return 0; } - bool inHtmTransactionalState() const override + bool + inHtmTransactionalState() const override { return instFlags[HtmFromTransaction]; } - uint64_t getHtmTransactionalDepth() const override + uint64_t + getHtmTransactionalDepth() const override { if (inHtmTransactionalState()) return this->htmDepth; @@ -578,14 +603,16 @@ class BaseDynInst : public ExecContext, public RefCounted return 0; } - void setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth) + void + setHtmTransactionalState(uint64_t htm_uid, uint64_t htm_depth) { instFlags.set(HtmFromTransaction); htmUid = htm_uid; htmDepth = htm_depth; } - void clearHtmTransactionalState() + void + clearHtmTransactionalState() { if (inHtmTransactionalState()) { DPRINTF(HtmCpu, @@ -645,7 +672,8 @@ class BaseDynInst : public ExecContext, public RefCounted int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); } int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); } int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); } - int8_t numVecElemDestRegs() const + int8_t + numVecElemDestRegs() const { return staticInst->numVecElemDestRegs(); } @@ -667,7 +695,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Pops a result off the instResult queue. * If the result stack is empty, return the default value. * */ - InstResult popResult(InstResult dflt = InstResult()) + InstResult + popResult(InstResult dflt=InstResult()) { if (!instResult.empty()) { InstResult t = instResult.front(); @@ -681,7 +710,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** @{ */ /** Scalar result. */ template - void setScalarResult(T&& t) + void + setScalarResult(T &&t) { if (instFlags[RecordResult]) { instResult.push(InstResult(std::forward(t), @@ -691,7 +721,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Full vector result. */ template - void setVecResult(T&& t) + void + setVecResult(T &&t) { if (instFlags[RecordResult]) { instResult.push(InstResult(std::forward(t), @@ -701,7 +732,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Vector element result. */ template - void setVecElemResult(T&& t) + void + setVecElemResult(T &&t) { if (instFlags[RecordResult]) { instResult.push(InstResult(std::forward(t), @@ -711,7 +743,8 @@ class BaseDynInst : public ExecContext, public RefCounted /** Predicate result. */ template - void setVecPredResult(T&& t) + void + setVecPredResult(T &&t) { if (instFlags[RecordResult]) { instResult.push(InstResult(std::forward(t), @@ -721,40 +754,46 @@ class BaseDynInst : public ExecContext, public RefCounted /** @} */ /** Records an integer register being set to a value. */ - void setIntRegOperand(const StaticInst *si, int idx, RegVal val) + void + setIntRegOperand(const StaticInst *si, int idx, RegVal val) override { setScalarResult(val); } /** Records a CC register being set to a value. */ - void setCCRegOperand(const StaticInst *si, int idx, RegVal val) + void + setCCRegOperand(const StaticInst *si, int idx, RegVal val) override { setScalarResult(val); } /** Record a vector register being set to a value */ - void setVecRegOperand(const StaticInst *si, int idx, - const VecRegContainer& val) + void + setVecRegOperand(const StaticInst *si, int idx, + const VecRegContainer &val) override { setVecResult(val); } /** Records an fp register being set to an integer value. */ void - setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) + setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) override { setScalarResult(val); } /** Record a vector register being set to a value */ - void setVecElemOperand(const StaticInst *si, int idx, const VecElem val) + void + setVecElemOperand(const StaticInst *si, int idx, + const VecElem val) override { setVecElemResult(val); } /** Record a vector register being set to a value */ - void setVecPredRegOperand(const StaticInst *si, int idx, - const VecPredRegContainer& val) + void + setVecPredRegOperand(const StaticInst *si, int idx, + const VecPredRegContainer &val) override { setVecPredResult(val); } @@ -766,7 +805,8 @@ class BaseDynInst : public ExecContext, public RefCounted void markSrcRegReady(RegIndex src_idx); /** Returns if a source register is ready. */ - bool isReadySrcRegIdx(int idx) const + bool + isReadySrcRegIdx(int idx) const { return this->_readySrcRegIdx[idx]; } @@ -921,10 +961,10 @@ class BaseDynInst : public ExecContext, public RefCounted } /** Read the PC state of this instruction. */ - TheISA::PCState pcState() const { return pc; } + TheISA::PCState pcState() const override { return pc; } /** Set the PC state of this instruction. */ - void pcState(const TheISA::PCState &val) { pc = val; } + void pcState(const TheISA::PCState &val) override { pc = val; } /** Read the PC of this instruction. */ Addr instAddr() const { return pc.instAddr(); } @@ -935,12 +975,10 @@ class BaseDynInst : public ExecContext, public RefCounted /**Read the micro PC of this instruction. */ Addr microPC() const { return pc.microPC(); } - bool readPredicate() const - { - return instFlags[Predicate]; - } + bool readPredicate() const override { return instFlags[Predicate]; } - void setPredicate(bool val) + void + setPredicate(bool val) override { instFlags[Predicate] = val; @@ -950,13 +988,13 @@ class BaseDynInst : public ExecContext, public RefCounted } bool - readMemAccPredicate() const + readMemAccPredicate() const override { return instFlags[MemAccPredicate]; } void - setMemAccPredicate(bool val) + setMemAccPredicate(bool val) override { instFlags[MemAccPredicate] = val; } @@ -968,7 +1006,7 @@ class BaseDynInst : public ExecContext, public RefCounted void setThreadState(ImplState *state) { thread = state; } /** Returns the thread context. */ - ThreadContext *tcBase() const { return thread->getTC(); } + ThreadContext *tcBase() const override { return thread->getTC(); } public: /** Returns whether or not the eff. addr. source registers are ready. */ @@ -991,28 +1029,48 @@ class BaseDynInst : public ExecContext, public RefCounted public: /** Returns the number of consecutive store conditional failures. */ - unsigned int readStCondFailures() const - { return thread->storeCondFailures; } + unsigned int + readStCondFailures() const override + { + return thread->storeCondFailures; + } /** Sets the number of consecutive store conditional failures. */ - void setStCondFailures(unsigned int sc_failures) - { thread->storeCondFailures = sc_failures; } + void + setStCondFailures(unsigned int sc_failures) override + { + thread->storeCondFailures = sc_failures; + } public: // monitor/mwait funtions - void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); } - bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); } - void mwaitAtomic(ThreadContext *tc) - { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); } - AddressMonitor *getAddrMonitor() - { return cpu->getCpuAddrMonitor(threadNumber); } + void + armMonitor(Addr address) override + { + cpu->armMonitor(threadNumber, address); + } + bool + mwait(PacketPtr pkt) override + { + return cpu->mwait(threadNumber, pkt); + } + void + mwaitAtomic(ThreadContext *tc) override + { + return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); + } + AddressMonitor * + getAddrMonitor() override + { + return cpu->getCpuAddrMonitor(threadNumber); + } }; template Fault BaseDynInst::initiateMemRead(Addr addr, unsigned size, Request::Flags flags, - const std::vector& byte_enable) + const std::vector &byte_enable) { assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest( @@ -1034,7 +1092,7 @@ template Fault BaseDynInst::writeMem(uint8_t *data, unsigned size, Addr addr, Request::Flags flags, uint64_t *res, - const std::vector& byte_enable) + const std::vector &byte_enable) { assert(byte_enable.empty() || byte_enable.size() == size); return cpu->pushRequest(