From: lkcl <lkcl@web>
Date: Mon, 2 Aug 2021 22:42:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~524
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a60cbc13770f55da11b1184f35db406bb8fccc36;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 4a7f41716..7211cebb2 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -17,7 +17,7 @@ including.
 The `BI` field of Branch Conditional operations is five bits,
 in scalar v3.0B this would select one bit of the 32 bit CR.
 In SVP64 there are 16 32 bit CRs, containing 128 4-bit CR Fields.
-Therefore, the 2 LSBs of `BI` select the bit from the CR, and the
+Therefore, the 2 LSBs of `BI` select the bit from the CR Field, and the
 top 3 bits are extended to either scalar or vector and to
 select CR Fields 0..127 as specified
 in SVP64 [[sv/svp64/appendix]]