From: Eric Botcazou Date: Wed, 30 Jun 2004 21:45:28 +0000 (+0200) Subject: sparc-protos.h (output_cbranch): Constify return value. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a6163c2238f5e27c5063727e75518de1e389bd04;p=gcc.git sparc-protos.h (output_cbranch): Constify return value. * config/sparc/sparc-protos.h (output_cbranch): Constify return value. (output_v9branch): Likewise. (sparc_v8plus_shift): Likewise. Rename into output_v8plus_shift. * config/sparc/sparc.c (output_cbranch): Constify return value. Prettify output for delay slots. (output_v9branch): Likewise. (sparc_v8plus_shift): Constify return value. Rename into output_v8plus_shift. * config/sparc/sparc.md (ashldi3_v8plus): Adjust call to sparc_v8plus_shift. (ashrdi3_v8plus): Likewise. (lshrdi3_v8plus): Likewise. (call_address_struct_value_sp32): Prettify output for delay slots. (call_symbolic_struct_value_sp32): Likewise. (call_address_untyped_struct_value_sp32): Likewise. (call_symbolic_untyped_struct_value_sp32): Likewise. From-SVN: r83934 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8244666a5cb..3ea59d6eb24 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2004-06-30 Eric Botcazou + + * config/sparc/sparc-protos.h (output_cbranch): Constify return + value. + (output_v9branch): Likewise. + (sparc_v8plus_shift): Likewise. Rename into output_v8plus_shift. + * config/sparc/sparc.c (output_cbranch): Constify return value. + Prettify output for delay slots. + (output_v9branch): Likewise. + (sparc_v8plus_shift): Constify return value. Rename into + output_v8plus_shift. + * config/sparc/sparc.md (ashldi3_v8plus): Adjust call to + sparc_v8plus_shift. + (ashrdi3_v8plus): Likewise. + (lshrdi3_v8plus): Likewise. + (call_address_struct_value_sp32): Prettify output for delay slots. + (call_symbolic_struct_value_sp32): Likewise. + (call_address_untyped_struct_value_sp32): Likewise. + (call_symbolic_untyped_struct_value_sp32): Likewise. + 2004-06-30 Zdenek Dvorak * common.opt (ftree-loop-optimize): New flag. diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 2f2ee5192e7..fc3e17fdda2 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -83,10 +83,11 @@ extern void sparc_emit_set_const64 (rtx, rtx); extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); extern int sparc_splitdi_legitimate (rtx, rtx); extern int sparc_absnegfloat_split_legitimate (rtx, rtx); -extern char *output_cbranch (rtx, rtx, int, int, int, int, rtx); +extern const char *output_cbranch (rtx, rtx, int, int, int, int, rtx); extern const char *output_return (rtx); extern const char *output_sibcall (rtx, rtx); -extern char *output_v9branch (rtx, rtx, int, int, int, int, int, rtx); +extern const char *output_v8plus_shift (rtx *, rtx, const char *); +extern const char *output_v9branch (rtx, rtx, int, int, int, int, int, rtx); extern void emit_v9_brxx_insn (enum rtx_code, rtx, rtx); extern void print_operand (FILE *, rtx, int); extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); @@ -110,7 +111,6 @@ extern int reg_unused_after (rtx, rtx); extern int register_ok_for_ldd (rtx); extern int registers_ok_for_ldd_peep (rtx, rtx); extern int v9_regcmp_p (enum rtx_code); -extern char *sparc_v8plus_shift (rtx *, rtx, const char *); /* Function used for V8+ code generation. Returns 1 if the high 32 bits of REG are 0 before INSN. */ extern int sparc_check_64 (rtx, rtx); diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index cf2526f7ef7..01530cfe2b7 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -5825,11 +5825,11 @@ sparc_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) INSN, if set, is the insn. */ -char * +const char * output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, int noop, rtx insn) { - static char string[50]; + static char string[64]; enum rtx_code code = GET_CODE (op); rtx cc_reg = XEXP (op, 0); enum machine_mode mode = GET_MODE (cc_reg); @@ -5845,7 +5845,7 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, to be,pn %xcc, .+12 - nop + nop ba .LC30 and @@ -5855,7 +5855,7 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, to fbe,pt %fcc2, .+16 - nop + nop ba .LC29 */ far = get_attr_length (insn) >= 3; @@ -6048,10 +6048,10 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, p = strchr (p, '\0'); if (far) { - strcpy (p, ".+12\n\tnop\n\tb\t"); + strcpy (p, ".+12\n\t nop\n\tb\t"); if (annul || noop) p[3] = '6'; - p += 13; + p += 14; } *p++ = '%'; *p++ = 'l'; @@ -6060,7 +6060,7 @@ output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, *p++ = label + '0'; *p = '\0'; if (noop) - strcpy (p, "\n\tnop"); + strcpy (p, "\n\t nop"); return string; } @@ -6289,11 +6289,11 @@ sparc_emit_fixunsdi (rtx *operands, enum machine_mode mode) NOOP is nonzero if we have to follow this branch by a noop. */ -char * +const char * output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, int annul, int noop, rtx insn) { - static char string[50]; + static char string[64]; enum rtx_code code = GET_CODE (op); enum machine_mode mode = GET_MODE (XEXP (op, 0)); rtx note; @@ -6308,7 +6308,7 @@ output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, to brz,pn %g1, .+12 - nop + nop ba,pt %xcc, .LC30 and @@ -6318,7 +6318,7 @@ output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, to brlz,pt %o1, .+16 - nop + nop ba,pt %xcc, .LC29 */ far = get_attr_length (insn) >= 3; @@ -6399,10 +6399,10 @@ output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, veryfar = 0; } - strcpy (p, ".+12\n\tnop\n\t"); + strcpy (p, ".+12\n\t nop\n\t"); if (annul || noop) p[3] = '6'; - p += 11; + p += 12; if (veryfar) { strcpy (p, "b\t"); @@ -6420,7 +6420,7 @@ output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, *p = '\0'; if (noop) - strcpy (p, "\n\tnop"); + strcpy (p, "\n\t nop"); return string; } @@ -7721,8 +7721,8 @@ sparc_check_64 (rtx x, rtx insn) /* Returns assembly code to perform a DImode shift using a 64-bit global or out register on SPARC-V8+. */ -char * -sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode) +const char * +output_v8plus_shift (rtx *operands, rtx insn, const char *opcode) { static char asm_code[60]; diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index f3ce4368e75..7f6c3fbead0 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -6978,7 +6978,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - { return sparc_v8plus_shift (operands, insn, "sllx"); } + "* return output_v8plus_shift (operands, insn, \"sllx\");" [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7095,7 +7095,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - { return sparc_v8plus_shift (operands, insn, "srax"); } + "* return output_v8plus_shift (operands, insn, \"srax\");" [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7184,7 +7184,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - { return sparc_v8plus_shift (operands, insn, "srlx"); } + "* return output_v8plus_shift (operands, insn, \"srlx\");" [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7435,7 +7435,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" - "call\t%a0, %1\n\tnop\n\tunimp\t%2" + "call\t%a0, %1\n\t nop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -7448,7 +7448,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0" - "call\t%a0, %1\n\tnop\n\tunimp\t%2" + "call\t%a0, %1\n\t nop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -7461,7 +7461,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\t%a0, %1\n\tnop\n\tnop" + "call\t%a0, %1\n\t nop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -7474,7 +7474,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\t%a0, %1\n\tnop\n\tnop" + "call\t%a0, %1\n\t nop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")])