From: Ali Saidi <saidi@eecs.umich.edu>
Date: Mon, 8 Oct 2007 19:19:58 +0000 (-0400)
Subject: Configuration: Move iocache outside of processors loop so it works for MP systems
X-Git-Tag: m5_2.0_beta4~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a630d77ec5cb208db5fe581f11ca2f7a01b3d7ce;p=gem5.git

Configuration: Move iocache outside of processors loop so it works for MP systems

--HG--
extra : convert_revision : 0ba563555a94eb22a6d4e402388e75e70d3556c2
---

diff --git a/configs/example/fs.py b/configs/example/fs.py
index ea525bf41..74ee875a3 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -119,16 +119,19 @@ if options.l2cache:
     test_sys.l2.mem_side = test_sys.membus.port
 
 test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
+
+if options.caches:
+    test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+    test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+    test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
+                       cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
+    test_sys.iocache.cpu_side = test_sys.iobus.port
+    test_sys.iocache.mem_side = test_sys.membus.port
+
 for i in xrange(np):
     if options.caches:
         test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                 L1Cache(size = '64kB'))
-        test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
-        test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
-        test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
-                           cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
-        test_sys.iocache.cpu_side = test_sys.iobus.port
-        test_sys.iocache.mem_side = test_sys.membus.port
     if options.l2cache:
         test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
     else: