From: Michael Meissner Date: Thu, 6 Feb 2020 23:39:48 +0000 (-0500) Subject: Fix PR 93569. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=a66219dce7fcba068a0998dd926e2ffc6857f149;p=gcc.git Fix PR 93569. 2020-02-06 Michael Meissner PR target/93569 * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 we only had X-FORM (reg+reg) addressing for vectors. Also before ISA 3.0, we only had X-FORM addressing for scalars in the traditional Altivec registers. --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aec58a06529..9797dd4e81f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2020-02-06 Michael Meissner + + PR target/93569 + * config/rs6000/rs6000.c (reg_to_non_prefixed): Before ISA 3.0 + we only had X-FORM (reg+reg) addressing for vectors. Also before + ISA 3.0, we only had X-FORM addressing for scalars in the + traditional Altivec registers. + 2020-02-06 Vladimir Makarov diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f2516a83842..fc68976bb10 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -24932,7 +24932,8 @@ reg_to_non_prefixed (rtx reg, machine_mode mode) unsigned size = GET_MODE_SIZE (mode); /* FPR registers use D-mode for scalars, and DQ-mode for vectors, IEEE - 128-bit floating point, and 128-bit integers. */ + 128-bit floating point, and 128-bit integers. Before power9, only indexed + addressing was available for vectors. */ if (FP_REGNO_P (r)) { if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode)) @@ -24945,16 +24946,20 @@ reg_to_non_prefixed (rtx reg, machine_mode mode) && (VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode) || mode == TImode || mode == CTImode)) - return NON_PREFIXED_DQ; + return (TARGET_P9_VECTOR) ? NON_PREFIXED_DQ : NON_PREFIXED_X; else return NON_PREFIXED_DEFAULT; } /* Altivec registers use DS-mode for scalars, and DQ-mode for vectors, IEEE - 128-bit floating point, and 128-bit integers. */ + 128-bit floating point, and 128-bit integers. Before power9, only indexed + addressing was available. */ else if (ALTIVEC_REGNO_P (r)) { + if (!TARGET_P9_VECTOR) + return NON_PREFIXED_X; + if (mode == SFmode || size == 8 || FLOAT128_2REG_P (mode)) return NON_PREFIXED_DS;